DatasheetsPDF.com

PLL650-06

PhaseLink

Network LAN Clock


Description
FEATURES w w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. One output fixed at 50MHz One selectable frequency output of 66.6 or 75MHz (with Double Drive Strength output). Zero PPM synthesis error in al...



PhaseLink

PLL650-06

File Download Download PLL650-06 Datasheet


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)