DatasheetsPDF.com

PLL650-05

PhaseLink
Part Number PLL650-05
Manufacturer PhaseLink
Description Low EMI Network LAN Clock
Published Feb 10, 2006
Detailed Description FEATURES • • • • w w• • • • • w • Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at T...
Datasheet PDF File PLL650-05 PDF File

PLL650-05
PLL650-05

Overview
FEATURES • • • • w w• • • • • w • Full CMOS output swing with 40-mA output drive capability.
25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
3 fixed outputs of 25MHz, 75Mhz and 125Mhz with output disable SDRAM selectable frequencies of 105, 83.
3, 140MHz (Double Drive Strength).
Spread spectrum technology selectable for EMI reduction from ±0.
5%, ±0.
75% center for SDRAM and CPU.
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.
3V operation.
Available in 16-Pin 150mil SOIC.
.
D at h S a t e e 4U .
m o c PLL650-05 Low EMI Network LAN Clock PIN CONFIGURATION XIN XOUT/ENB_125M*^ GND VDD 125MH...


Similar Datasheet


Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)