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Texas Instruments |
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the posit |
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Hitachi Semiconductor |
Octal D-type Flip-Flops (with 3-state outputs) • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (D to Q, Q) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input |
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Hitachi Semiconductor |
Octal D-type Flip Flops with 3-state Outputs • • • • • • VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 °C) Typical VOH undershoot > 2.0 V (@VCC = |
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Fairchild Semiconductor |
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops s Choice of 8 latches or 8 D-type flip-flops in a single package s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P inputs reduce D-C loading on data lines Ordering Code: Order Number DM74LS373WM DM74L |
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nexperia |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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NXP |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of cl |
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IK Semiconductor |
Octal D-Type Flip-Flop IN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Pow |
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NXP |
Octal D-type flip-flop a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-im |
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Texas Instruments |
Octal Edge-Triggered D-Type Flip-Flops • Wide Operating Voltage Range of 2 V to 6 V • High-Current 3-State True Outputs Can Drive Up to 15 LSTTL Loads • Eight D-Type Flip-Flops in a Single Package • Full Parallel Access for Loading • Low Power Consumption, 80-µA Max ICC • Typical tpd = 14 |
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NXP |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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National Semiconductor |
TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Y Y Y Y Y Choice of 8 latches or 8 D-type flip-flops in a single package TRI-STATE bus-driving outputs Full parallel-access for loading Buffered control inputs P-N-P inputs reduce D-C loading on data lines Connection Diagrams Dual-In-Line Packages |
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nexperia |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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Texas Instruments |
Octal D-Type EDGE-Triggered Flip-Flop 3-state outputs designed for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ′ACT11534 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q output |
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Texas Instruments |
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driv |
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Texas Instruments |
Octal D-Type Flip-Flop Description • Buffered Inputs • Common Three-State Output Enable Control • Three-State Outputs • Bus Line Driving Capability • Typical Propagation Delay (Clock to Q) = 15ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Stand |
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Renesas |
Octal D-type Positive-edge-triggered Flip-Flops • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS273P DILP-20 pin PRDP0020AC-B (DP-20NEV) P HD74LS273FPEL SOP-20 pin (JEITA) PRSP0020DD-B FP (FP-20DAV) HD74LS273RPEL SOP-20 pin (JEDEC |
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National Semiconductor |
Octal D-Type Flip-Flop n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n See ’ABT273 for master reset version n See ’ABT373 for transparent latch version n See ’ABT374 for TRI-STATE® version n Ou |
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Fairchild Semiconductor |
Octal D-Type Flip-Flop s Ideal buffer for microprocessor or memory s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous master reset s See 377 for clock enable version s See 373 for transparent latch version s See 374 for 3-STATE versio |
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Fairchild Semiconductor |
Octal D-Type Flip-Flops s Typical propagation delay: 18 ns s Wide operating voltage range s Low input current: 1 µA maximum s Low quiescent current: 80 µA (74 Series) s Output drive: 10 LS-TTL loads Ordering Code: Order Number MM74HC273M MM74HC273SJ MM74HC273MTC MM74HC273N |
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NXP |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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