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SAB82520

Siemens

High-Level Serial Communications Controller


SAB82520
SAB82520

PDF File SAB82520 PDF File


Description
High-Level Serial Communications Controller (HSCC) 1 Features Two independent HDLC channels Implementation of X.
25 LAPB/LAPD protocol Programmable timeout and retry conditions FIFO buffers for efficient transfer of data packets Digital phase-locked loop for each channel Baudrate generator and oscillator Different modes for clock recovery and data encoding High-speed data rate (up to 4 MHz) Supports bus configuration by collision resolution Telecom-specific features programmable 8-bit parallel µP interface Advanced CMOS technology Low power consumption; active: 25 mW at 4 MHz standby: 3 mW SAB 82520: operating temperature 0 to 70 ˚C SAF 82520: operating temperature – 40 to 85 ˚C SAB 82520 SAF 82520 P-LCC-28-R P-DIP-28 SAB 82520, a High-level Serial Communications Controller (HSCC), has been designed to free the user from tasks occurring in communication via networks and trunk lines.
SAB 82520 is an X.
25 LAPB/LAPD controller which, to a large degree performs communications procedures independently of CPU support.
A parallel processor bus constitutes the µC system.
The communications interface is implemented by two full-duplex HDLC channels, which can be operated independently from one another.
The HSCC is connected to the transmission line via additional line drivers or modems.
External logic is cost-effective because clock recovery can be performed by an onchip oscillator, DPLL circuits and a programmable baudrate generator.
Type SAB 82520-N SAB 82520-P SAF 82520-N SAF 82520-P Ordering Code Q67100-H8400 Q67100-H8014 Q67100-H8610 Q67100-H8512 Package P-LCC-28 (SMD) P-DIP-28 P-LCC-28 (SMD) P-DIP-28 Semiconductor Group 5 03.
94 SAB 82520 SAF 82520 Figure 1 Logic Symbol Semiconductor Group 6 SAB 82520 SAF 82520 Pin Configurations (top view) P-DIP P-LCC Figure 2 Semiconductor Group 7 SAB 82520 SAF 82520 1.
1 Pin Definitions and Functions Pin No.
Symbol 25 26 27 28 1 2 3 4 5 12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 RTSA RTSB Input (I) Output (O) I/O I/O I/O I/O I...



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