Dual UTrenchMOS logic level FET
Description
PMGD8000LN
Dual µTrenchMOS™ logic level FET
MBD128
www.
DataSheet4U.
com
Rev.
01 — 27 February 2003
Product data
1.
Description
Dual N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology.
Product availability: PMGD8000LN in SOT363 (SC-88).
2.
Features
s s s s TrenchMOS™ technology Very fast switching Logic level compatible Subminiature surface mount package.
3.
Applications
s Battery management s High-speed switch s Low power DC-to-DC converter.
4.
Pinning information
Table 1: Pin 1 2 3 4 5 6 Pinning - SOT363 (SC-88), simplified outline and symbol Description source (s1) gate (g1) drain (d2) source (s2) gate (g2) drain (d1)
1 Top view 2 3
MSA370
Simplified outline
6 5 4
Symbol
d1 d2
s1
g1
s2
g2
MSD901
SOT363 (SC-88)
Philips Semiconductors
PMGD8000LN
www.
DataSheet4U.
com Dual µTrenchMOS™ logic level FET
5.
Quick reference data
Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions 25 °C ≤ Tj 150 °C Tamb = 25 °C; VGS = 4 V Tamb = 25 °C VGS = 4 V; ID = 10 mA VGS = 2.
5 V; ID = 1 mA Typ 1.
8 2.
9 Max 30 125 0.
2 150 8 13 Unit V mA W °C Ω Ω drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter
6.
Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter VDS VGS ID IDM Ptot Tstg Tj IS drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tamb = 25 °C Tamb = 25 °C; VGS = 4 V; Figure 2 and 3 Tamb = 70 °C; VGS = 4 V; Figure 2 Tamb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tamb = 25 °C; Figure 1 Conditions 25 °C ≤ Tj 150 °C Min −55 −55 Max 30 ±15 125 100 250 0.
2 +150 +150 125 Unit V V mA mA mA W °C °C mA
Source-drain diode
9397 750 10939
© Koninklijke Philips Electronics N.
V.
2003.
All rights reserved.
Product data
Rev.
01 — 27 Feb...
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