(IDT7236x3) CMOS SyncFIFO WITH BUS-MATCHING
Description
CMOS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36 4,096 x 36 8,192 x 36
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IDT723653 IDT723663 IDT723673
FEATURES
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Memory storage capacity: IDT723653 – 2,048 x 36 IDT723663 – 4,096 x 36 IDT723673 – 8,192 x 36 Clock frequencies up to 83 MHz (8 ns access time) Clocked FIFO buffering data from Port A to Port B IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions) Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024) Serial or parallel programming of partial flags Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)
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Big- or Little-Endian format for word and byte bus sizes Retransmit Capability Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Easily expandable in width and depth Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin compatible with the lower density parts, IDT723623/723633/ 723643 Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
MBF1 Mail 1 Register Port-A Control Logic
BusMatching Input Register Output Register
36
CLKA CSA W/RA ENA MBA RS1 RS2 PRS
RAM ARRAY
36
FIFO1 Mail1, Mail2, Reset Logic
36
2,048 x 36 4,096 x 36 8,192 x 36
36
RT RTM
FIFO Retransmit Logic
Write Pointer
Read Pointer B0-B35
A0-A35
FF/IR AF
Status Flag Logic
EF/OR AE
36
36
FS2 FS0/SD FS1/SEN
Programmable Flag Offset Registers
13
Timing Mode
Port-B Control Logic Mail 2 Register MBF2
FWFT CLKB CSB W/RB ENB MBB BE BM SIZE
5610 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
SyncFIFO is a trademark of Integrated Device Technology, Inc.
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