LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER
Description
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC100ES7111/D Rev 0, 12/2002 www.
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Preliminary Information
Low Voltage 1:10 Differential LVDS Clock Fanout Buffer
The Motorola MC100ES7111 is a LVDS differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES7111 supports various applications that require the distribution of precisely aligned differential clock signals.
Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics.
Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems.
MC100ES7111
LOW–VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK FANOUT DRIVER
• • • • • • • • •
Features: 1:10 differential clock fanout buffer 50 ps maximum device skew1 SiGe technology Supports DC to 1000 MHz operation1 of clock or data signals LVDS compatible differential clock outputs PECL and HSTL/LVDS compatible differential clock inputs 3.
3V power supply Supports industrial temperature range Standard 32 lead LQFP package
FA SUFFIX 32–LEAD LQFP PACKAGE CASE 873A
Functional Description The MC100ES7111 is designed for low skew clock distribution systems and supports clock frequencies up to 1000 MHz1.
The device accepts two clock sources.
The CLK0 input accepts LVDS or HSTL compatible signals and CLK1 accepts PECL compatible signals.
The selected input signal is distributed to 10 identical, differential LVDS compatible outputs.
The output enable control is synchronized internally preventing output runt pulse generation.
Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high).
The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal.
The device is packaged in a 7x7 mm2 32-lead LQFP package.
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