TrenchMOS logic level FET
Description
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BUK95/96/9E4R4-40B
TrenchMOS™ logic level FET
Rev.
02 — 13 October 2003 Product data
1.
Product profile
1.
1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using Philips High-Performance Automotive (HPA) TrenchMOS™ technology.
1.
2 Features
s Very low on-state resistance s 175 °C rated s Q101 compliant s Logic level compatible.
1.
3 Applications
s Automotive systems s Motors, lamps and solenoids s 12 V loads s General purpose power switching.
1.
4 Quick reference data
s EDS(AL)S ≤ 961 mJ s ID ≤ 75 A s RDSon = 3.
9 mΩ (typ) s Ptot ≤ 254 W.
2.
Pinning information
Table 1: Pin 1 2 3 mb Pinning - SOT78, SOT404, and SOT226 simplified outlines and symbol Description gate (g) drain (d) source (s) mounting base, connected to drain (d)
2 1
MBK106
Simplified outline
[1]
Symbol
mb mb d
mb
g s
MBB076
3
MBK116
1 2 3
MBK112
1 2 3
SOT78 (TO-220AB)
[1]
SOT404 (D2-PAK)
SOT226 (I2-PAK)
It is not possible to make connection to pin 2 of the SOT404 package.
Philips Semiconductors
www.
DataSheet4U.
com
BUK95/96/9E4R4-40B
TrenchMOS™ logic level FET
3.
Ordering information
Table 2: Ordering information Package Name BUK954R4-40B BUK964R4-40B BUK9E4R4-40B TO-220AB D2-PAK I2-PAK Description Plastic single-ended heat-sink mounted package Plastic single-ended surface mounted package Plastic single-ended low-profile package Version SOT78 SOT404 SOT226 Type number
4.
Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter VDS VDGR VGS ID drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 5 V; Figure 2 IDM Ptot Tstg Tj IDR IDRM peak drain current total power dissipation storage temperature junction temperature reverse drain current (DC) peak reverse drain current Tmb = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 75 A; VDS ≤ 40 V; V...
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