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DFP2INT

Digital Core Design

Floating Point To Integer Pipelined Converter


DFP2INT
DFP2INT

PDF File DFP2INT PDF File


Description
DFP2INT Floating Point To Integer Pipelined Converter www.
DataSheet4U.
com ver 2.
20 OVERVIEW The DFP2INT is the pipelined floating point to integer converter.
The input and output numbers format is according to IEEE-754 standard.
DFP2INT supports single precision real numbers and double word integers (4 Bytes).
Convert operation is pipelined to 2 levels.
Input data are fed every clock cycle.
The first result appears after latency equal to 2 clock periods and next results are available each clock cycle.
Full precision and accuracy are accomplished.
● Fully synthesizable, static synchronous design with no internal tri-states DELIVERABLES ♦ Source code: ◊ VHDL Source Code or/and ◊ VERILOG Source Code or/and ◊ Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet Synthesis scripts Example application Technical support ◊ IP Core implementation support ◊ 3 months maintenance ● ● ● ♦ APPLICATION ● ● ● ● Math coprocessors DSP algorithms Embedded arithmetic coprocessor Data processing & control ♦ ♦ ♦ ♦ KEY FEATURES ● ● ● ● ● ● ● ● ● ● Full IEEE-754 compliance Single precision real input numbers Double word output numbers(4 Bytes) Simple interface No programming required 2 levels pipelining Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply.
Single Design license allows using IP Core in single FPGA bitstream and ASIC implementation.
It also permits FPGA prototyping before ASIC production.
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