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A6832

Allegro MicroSystems
Part Number A6832
Manufacturer Allegro MicroSystems
Published Feb 15, 2007
Description DABiC-5 32-Bit Serial Input Latched Sink Drivers
Detailed Description A6832 DABiC-5 32-Bit Serial Input Latched Sink Drivers Features and Benefits ▪ 3.3 to 5 V logic supply range ▪ To 10 MH...
Datasheet PDF File A6832 PDF File

A6832
A6832


Overview
A6832 DABiC-5 32-Bit Serial Input Latched Sink Drivers Features and Benefits ▪ 3.
3 to 5 V logic supply range ▪ To 10 MHz data input rate ▪ Schmitt trigger inputs for improved noise immunity ▪ Low-power CMOS logic and latches ▪ 40 V current sink outputs ▪ Low saturation voltage ▪ –40°C operation available Applications: ▪ Thermal printheads ▪ Multiplexed LED displays ▪ Incandescent lamps Package: 44-pin PLCC (suffix EP) 18 6 19 5 20 4 21 3 22 2 23 1 24 44 25 43 26 42 27 41 28 40 Not to scale 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 Description Intended originally to drive thermal printheads, the A6832 has been optimized for low output-saturation voltage, high-speed operation, and pin configurations that are the most convenient for the tight space requirements of high-resolution printheads.
These integrated circuits can also be used to drive multiplexed LED displays or incandescent lamps at up to 125 mA peak current.
The combination of bipolar and MOS technologies gives theA6832 arrays an interface flexibility beyond the reach of standard buffers and power driver circuits.
The devices each have 32 bipolar NPN open-collector saturated drivers, a CMOS data latch for each of the drivers, two 16-bit CMOS shift registers, and CMOS control circuitry.
The highspeed CMOS shift registers and latches allow operation with most microprocessor-based systems.
Use of these drivers with TTLmay require input pull-up resistors to ensure an input logic high.
MOS serial data outputs permit cascading for interface applications requiring additional drive lines.
The A6832 is supplied in a 44-lead plastic leaded chip carrier, for surface-mount applications requiring minimum area.
These devices are lead (Pb) free, with 100% matte tin plated leadframes.
CLOCK S E R IAL DATA IN S TR OBE OUTPUT E NABLE Functional Block Diagram 32-BIT S HIFT R E G IS TE R LAT C HE S V DD S E R IAL DATA OUT MOS B IP O LAR 26185.
110G O UT1 O UT2 O UT3 G R O UND O UT30 O UT31 O UT32 ...


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