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MC74LVX245

Motorola

LOW-VOLTAGE CMOS - Motorola


MC74LVX245
MC74LVX245

PDF File MC74LVX245 PDF File



Description
www.
DataSheet4U.
com MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal Bus Transceiver With 5V-Tolerant Inputs The MC74LVX245 is an advanced high speed CMOS octal bus transceiver.
It is intended for two–way asynchronous communication between data buses.
The direction of data transmission is determined by the level of the T/R input.
The output enable pin (OE) can be used to disable the device, so that the buses are effectively isolated.
All inputs are equipped with protection circuits against static discharge.
MC74LVX245 LOW–VOLTAGE CMOS LVX • • • • • • • • High Speed: tPD = 4.
7ns (Typ) at VCC = 3.
3V Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Low Noise: VOLP = 0.
8V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V DW SUFFIX 20–LEAD SOIC PACKAGE CASE 751D–04 APPLICATION NOTES 1.
Do not force a signal on an I/O pin when it is an active output, damage may occur.
2.
All floating (high impedence) input or I/O pins must be fixed by means of pull up or pull down resistors or bus terminator ICs.
3.
A parasitic diode is formed between the bus and VCC terminals.
Therefore, the LVX245 cannot be used to interface 5V to 3V systems directly.
DT SUFFIX 20–LEAD TSSOP PACKAGE CASE 948E–02 VCC 20 OE 19 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 M SUFFIX 20–LEAD SOIC EIAJ PACKAGE CASE 967–01 PIN NAMES Pins 1 T/R 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 A6 9 A7 10 GND OE T/R A0–A7 B0–B7 Function Output Enable Input Transmit/Receive Input Side A 3–State Inputs or 3–State Outputs Side B 3–State Inputs or 3–State Outputs Figure 1.
20–Lead Pinout (Top View) 6/97 © Motorola, Inc.
1997 1 REV 0 DataSheet 4 U .
com www.
DataSheet4U.
com MC74LVX245 OE 19 T/R 1 2 18 A1 3 17 A2 4 16 A3 5 15 A4 6 14 A5 7 13 A6 8 12 A7 9 11 A0 B0 B1 B2 B3 B4 B5 B6 B7 Figure 2.
Logic Diagram INPUTS OE L L H T/R...



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