General Purpose SDRAM Controller
Description
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General-Purpose SDRAM Controller
SD R A M Co n t r o l l er Fu nc t i o na l D es cr i p t i o n
The general-purpose SDRAM controller is designed to provide simplified control of many different sizes of SDRAMs.
The controller architecture provides control for data bursts by linearly incrementing the address.
The user starts a burst at a specified address and the burst continues until the user terminates it.
SD R A M Co n t r o l l er Si g na l s
CLK RESET_N ACTIVATE WR_CYC ADDR CYC_DONE WR_BE_DONE RD_BE_DONE
RD_BE_RDY WR_BE_RDY MADDR CSn RASn CASn WEn BA DQM CKE
The SDRAM controller communicates with a user’s functions and drives the control signals into the SDRAM.
When the controller recognizes the start of a write cycle, the controller prepares the SDRAM to accept data and then indicates readiness by driving the WR_BE_RDY signal.
When the controller recognizes the start of a read cycle, the controller prepares the SDRAM to provide data and then indicates readiness by driving the RD_BE_RDY signal.
The WR_BE_RDY and RD_BE_RDY signals are one-stage pipelined.
On write cycles, the WR_BE_RDY signal is asserted one clock cycle prior to the time when data can actually be accepted by the SDRAM.
On read cycles, the RD_BE_RDY signal is asserted one clock cycle prior to the time when SDRAM data is valid.
In general, the *_RDY signals indicate that the SDRAM and controller will ready for data transfer on the next cycle.
Table 1 • SDRAM Controller Signals
Name Inputs from the User’s System Clk RESETn ACTIVATE WR_CYC ADDR(M:0) CYC_DONE WR_BE_NOW RD_BE_NOW
Figure 1 • SDRAM Controller The user provides a WR_BE_NOW and RD_BE_NOW signal to the controller.
When WR_BE_RDY and WR_BE_NOW are both asserted at the same time, or when RD_BE_RDY and RD_BE_NOW are both asserted at the same time, data is transferred.
If the WR_BE_NOW signal is not asserted, the controller will retain its current address until the WR_BE_NOW signal asserts at which time data is transferred.
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