40Msps / 12-Bit ADC
Description
19-3259; Rev 0; 5/04
KIT ATION EVALU E L B AVAILA
40Msps, 12-Bit ADC
General Description Features
o Excellent Dynamic Performance 68.
6dB SNR at fIN = 20MHz 90dBc SFDR at fIN = 20MHz o Low-Power Operation 159mW at 3.
0V (Single-Ended Clock) 181mW at 3.
3V (Single-Ended Clock) 198mW at 3.
3V (Differential Clock) o Differential or Single-Ended Clock o Accepts 20% to 80% Clock Duty Cycle o Fully Differential or Single-Ended Analog Input o Adjustable Full-Scale Analog Input Range o Common-Mode Reference o Power-Down Mode o CMOS-Compatible Outputs in Two’s Complement or Gray Code o Data-Valid Indicator Simplifies Digital Design o Out-of-Range and Data-Valid Indicators o Miniature, 40-Pin Thin QFN Package with Exposed Paddle o Pin-Compatible, IF Sampling ADC Available (MAX1211ETL) o Evaluation Kit Available (Order MAX1211EVKIT)
MAX1206
The MAX1206 is a 3.
3V, 12-bit analog-to-digital converter (ADC) featuring a fully differential wideband track-andhold (T/H) input, driving the internal quantizer.
The MAX1206 is optimized for low power, small size, and high dynamic performance.
This ADC operates from a single 3.
0V to 3.
6V supply, consuming only 159mW, while delivering a typical signal-to-noise ratio (SNR) performance of 68.
6dB at a 20MHz input frequency.
The T/H-driven input stage accepts single-ended or differential inputs.
In addition to low operating power, the MAX1206 features a 0.
15mW power-down mode to conserve power during idle periods.
A flexible reference structure allows the MAX1206 to use its internal precision bandgap reference or accept an externally applied reference.
A common-mode reference is provided to simplify design and reduce external component count in differential analog input circuits.
The MAX1206 supports both a single-ended and differential input clock drive.
Wide variations in the clock duty cycle are compensated with the ADC’s internal duty-cycle equalizer.
The MAX1206 features parallel, CMOS-compatible outputs.
The digital output format is pin s...
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