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MACHLV210-12

Lattice

High Density EE CMOS Programmable Logic


Description
FINAL COM’L: -12/15/20 IND: -18/24 MACHLV210-12/15/20 High Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s Low-voltage operation, 3.3-V JEDEC compatible — VCC = +3.0 V to +3.6 V s < 5 mA standby current s Patented design allows minimal standby current without speed degradation s Exclusively designed for 3.3-V applications s 44 Pins s 64 M...



Lattice

MACHLV210-12

PDF File MACHLV210-12 PDF File


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