High Speed Dual Type D Master-Slave Flip-Flop
Description
MC10231 High Speed Dual Type D Master-Slave Flip-Flop
The MC10231 is a dual master–slave type D flip–flop.
Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs.
Each flip–flop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function.
If the common clock is to be used to clock the flip–flop, the Clock Enable inputs must be in the low state.
In this case, the enable inputs perform the function of controlling the common clock.
The output states of the flip–flop change on the positive transition of the clock.
A change in the information present at the data (D) input will not affect the output information at any other time due to master–slave construction.
• PD = 270 mW typ/pkg (No Load) • tpd = 2 ns typ • tTog = 225 MHz typ • tr, tf = 2.
0 ns typ (20%–80%)
LOGIC DIAGRAM
S1 5 D1 7 CE1 6 Q1 Q1 R1 4 CC 9 R2 13 Q2 CE2 11 D2 10 S2 12 Q2 2 3 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 15 14
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com MARKING DIAGRAMS
16 CDIP–16 L SUFFIX CASE 620 1 16 PDIP–16 P SUFFIX CASE 648 1 1 PLCC–20 FN SUFFIX CASE 775 10231 AWLYYWW MC10231P AWLYYWW MC10231L AWLYYWW
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
DIP PIN ASSIGNMENT
VCC1 Q1 Q1 R1 S1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q2 Q2 R2 S2 CE2 D2 CC
CLOCKED TRUTH TABLE
C L H H D X L H Qn+1 Qn L H
R–S TRUTH TABLE
R L L H H S L H L H Qn+1 Qn H L N.
D.
CE1 D1 VEE
C = CE + CC.
A clock H is a clock transition from a low to a high state.
N.
D.
= Not Defined
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
ORDERING INFORMATION
Device MC10231L MC10231P MC10231FN Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev.
7
Publication Order Number: MC10231/D
MC10231
ELECTRICAL C...
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