64Mb H-die SDRAM Specification
Description
SDRAM 64Mb H-die (x4, x8, x16)
CMOS SDRAM
64Mb H-die SDRAM Specification
Revision 1.
4 November 2003
* Samsung Electronics reserves the right to change products or specification without notice.
Rev.
1.
4 November 2003
SDRAM 64Mb H-die (x4, x8, x16)
Revision History Revision 0.
0 (May, 2003)
• Target spec release
CMOS SDRAM
Revision 0.
1 (July, 2003)
• Preliminary spec release
Revision 0.
2 (August, 2003)
• Modified IBIS characteristic.
Revision 1.
0 (September, 2003)
• Finalized
Revision 1.
1 (September, 2003)
• Corrected IBIS Specification.
Revision 1.
2 (October, 2003)
• Deleted speed 7C at x4/x8.
Revision 1.
3 (October, 2003)
• Deleted AC parameter notes 5.
Revision 1.
4 (November, 2003)
• Modified Pin Function description.
Rev.
1.
4 November 2003
SDRAM 64Mb H-die (x4, x8, x16)
CMOS SDRAM
4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.
3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Burst read single-bit write operation • DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh • 64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
K4S640432...
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