64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
Description
K4S640832D
CMOS SDRAM
64Mbit SDRAM
2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.
0 June 1999
* Samsung Electronics reserves the right to change products or specification without notice.
Rev.
0.
0 May 1999
K4S640832D
2M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
• • • • JEDEC standard 3.
3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S640832D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
• • • • •
ORDERING INFORMATION
Part No.
K4S640832D-TC/L75 K4S640832D-TC/L80 K4S640832D-TC/L1H K4S640832D-TC/L1L Max Freq.
133MHz(CL=3) 125MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54 TSOP(II) Interface Package
K4S640832D-TC/L10 66MHz(CL=2 &3)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE LDQM
Data Input Register
Bank Select 2M x 8 Sense AMP 2M x 8 2M x 8 2M x 8 Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col.
Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS Timing Register
Programming Register LWCBR LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev.
0.
0 May 1999
K4S640832D
PIN CONFIGURATION (...
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