3.3V CMOS OCTAL D REGISTERS (3-STATE)
Description
3.
3V CMOS OCTAL D REGISTERS (3-STATE)
Integrated Device Technology, Inc.
IDT54/74FCT3574/A ADVANCE INFORMATION
FEATURES:
• 0.
5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • 25 mil Center SSOP Packages • Extended commercial range of -40°C to +85°C • VCC = 3.
3V ± 0.
3V, Normal Range or VCC = 2.
7V to 3.
6V, Extended Range • CMOS power levels (0.
4µW typ.
static) • Rail-to-Rail output swing for increased noise margin • Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The FCT3574/A are 8-bit registers built using an advanced dual metal CMOS technology.
These registers consist of eight D-type flip-flops with a buffered common clock and buffered 3-state output control.
When the output (OE) input is LOW, the eight outputs are enabled.
When the OE input is HIGH, the outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements of the D inputs is transferred to the O outputs on the LOW-toHIGH transition of the clock input.
FUNCTIONAL BLOCK DIAGRAM
D0 CP CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q D1 D2 D3 D4 D5 D6 D7
OE O0 O1 O2 O3 O4 O5 O6 O7
3095 drw 01
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 P20-1 5 D20-1 SO20-2 6 & 7 SO20-7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC O0 O1 O2 O3 O4 O5 O6 O7 CP
PIN DESCRIPTION
Pin Names DN CP ON Description D flip-flop data inputs Clock Pulse for the register.
Enters data on LOW-to-HIGH transition.
3-state outputs, (true) 3-state outputs, (inverted) Active LOW 3-state Output Enable input
3095 tbl 01
ON OE
DIP/SOIC/SSOP TOP VIEW
3095 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
AUGUST 1995
DSC-4650/-
8.
14
1
IDT54/74FCT3574/3574A 3.
3V CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (1)
Inputs Function
HI-Z LOAD REGISTER
...
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