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74AHCT595

NXP

8-bit serial-in/serial or parallel-out shift register


74AHCT595
74AHCT595

PDF File 74AHCT595 PDF File


Description
INTEGRATED CIRCUITS DATA SHEET 74AHC595; 74AHCT595 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product specification File under Integrated Circuits, IC06 2000 Mar 15 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 °C and from−40 to +125 °C.
APPLICATIONS • Serial-to-parallel data conversion • Remote control holding register.
DESCRIPTION 74AHC595; 74AHCT595 The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard No.
7A.
The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs.
The shift register has separate clocks.
Data is shifted on the positive-going transitions of the SHCP input.
The data in each register is transferred to the storage register on a positive-going transition of the STCP input.
If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages.
The storage register has 8 parallel 3-state bus driver outputs.
Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.
0 ns.
TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay SHCP to Q7’ STCP to Qn MR to Q7’ CI fmax CPD Notes 1.
CPD is used t...



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