Quadruple Bus Buffer Gate
Description
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FEATURES
• Controlled Baseline
– One Assembly/Test Site, One Fabrication Site
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification • Qualification Pedigree (1) • Operates From 1.
65 V to 3.
6 V • Inputs Accept Voltages to 5.
5 V • Max tpd of 4.
8 ns at 3.
3 V • Typical VOLP (Output Ground Bounce) <0.
8 V
at VCC = 3.
3 V, TA = 25°C
(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.
Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
SN74LVC125A-EP QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCAS739C – DECEMBER 2003 – REVISED DECEMBER 2006
• Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.
3 V, TA = 25°C
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
PW PACKAGE (TOP VIEW)
1OE 1 1A 2 1Y 3
2OE 4 2A 5 2Y 6
GND 7
14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y
DESCRIPTION/ORDERING INFORMATION
This quadruple bus buffer gate is designed for 1.
65-V to 3.
6-V VCC operation.
The SN74LVC125A features independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.
3-V or 5-V devices.
This feature allows the use of this device as a translator in a mixed 3.
3-V/5-V system environment.
TA –40°C to 85°C
–55°C t...
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