Synchronous DRAM Memory 128Mbit (8M x 16bit)
Description
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O
Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No.
History
1.
0 First Version Release
1.
1 1.
Corrected PIN ASSIGNMENT A12 to NC
1.
2
1.
Changed IDD3P and IDD3PS 3mA to 5mA 2.
Added Industrial Temperature (-40oC to 85oC)
1.
3 Changed tOH(Only Symbol ‘H’): 2.
5ns -> 2.
7ns
1.
4 Add Super Low Power-> IDD6: 500uA
Draft Date Dec.
2004 Jan.
2005 Feb.
2005 Apr.
2005 Aug.
2005
Remark
This document is a general product description and is subject to change without notice.
Hynix Semiconductor does not assume any
responsibility for use of circuits described.
No patent licenses are implied.
Rev.
1.
4 / Aug.
2005
1
Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L/S)T(P) Series
DESCRIPTION
The Hynix HY57V281620E(L/S)T(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth.
HY57V281620E(L/S)T(P) series is organiz...
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