PHASE CONTROL THYRISTOR
Description
POSEICO
POSEICO SPA POwer SEmiconductors Italian COrporation
POSEICO SPA Via N.
Lorenzi 8, 16152 Genova - ITALY Tel.
++ 39 010 6556234 - Fax ++ 39 010 6557519 Sales Office: Tel.
++ 39 010 6556775 - Fax ++ 39 010 6442510
PHASE CONTROL THYRISTOR
AT505
Repetitive voltage up to Mean on-state current Surge current 1600 V 430 A 5.
6 kA
FINAL SPECIFICATION
gen 03 - ISSUE : 05
Symbol
Characteristic
Conditions
Tj [°C]
125 125 125
Value
Unit
BLOCKING
V V V I I
RRM RSM DRM RRM DRM
Repetitive peak reverse voltage Non-repetitive peak reverse voltage Repetitive peak off-state voltage Repetitive peak reverse current Repetitive peak off-state current V=VRRM V=VDRM
1600 1700 1600 30 30
V V V mA mA
125 125
CONDUCTING
I I I V V r
T (AV) T (AV) TSM
Mean on-state current Mean on-state current Surge on-state current I² t On-state voltage Threshold voltage On-state slope resistance
180° sin, 50 Hz, Th=55°C, double side cooled 180° sin, 50 Hz, Tc=85°C, double side cooled sine wave, 10 ms without reverse voltage On-state current = 800 A 25 125 125 125
430 340 5.
6 157 x1E3 1.
55 1.
0 0.
680
A A kA A²s V V mohm
I² t
T T(TO) T
SWITCHING
di/dt dv/dt td tq Q rr I rr I I
H L
Critical rate of rise of on-state current, min.
Critical rate of rise of off-state voltage, min.
Gate controlled delay time, typical Circuit commutated turn-off time, typical Reverse recovery charge Peak reverse recovery current Holding current, typical Latching current, typical
From 75% VDRM up to 450 A, gate 10V 5ohm Linear ramp up to 70% of VDRM VD=100V, gate source 10V, 10 ohm , tr=.
5 µs dV/dt = 20 V/µs linear up to 75% VDRM di/dt=-20 A/µs, I= 290 A VR= 50 V VD=5V, gate open circuit VD=5V, tp=30µs
125 125 25 125 25 25
200 500 1.
6 200
A/µs V/µs µs µs µC A
300 700
mA mA
GATE
V I V V I V P P
GT GT GD FGM FGM RGM GM G
Gate trigger voltage Gate trigger current Non-trigger gate voltage, min.
Peak gate voltage (forward) Peak gate current Peak gate voltage (reverse) Peak gate power dissipation Average g...
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