CMOS Gate Array
Description
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Description IDTX3 is a non-inverting, TTL-level, input buffer piece.
Logic Symbol
Truth Table
IDTX3
QC P PADM D
PADM QC LL HH
®
Pin Loading Load
PADM 4.90 pF
HDL Syntax Verilog .................... IDTX3 inst_name (QC, PADM); VHDL...................... inst_name: IDTX3 port map (QC, PADM);
Power Characteristic...
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