N-channel transistor
Description
DISCRETE SEMICONDUCTORS
DATA SHEET
BST82 N-channel enhancement mode vertical D-MOS transistor
Product specification File under Discrete Semiconductors, SC13b April 1995
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
DESCRIPTION N-channel enhancement mode vertical D-MOS transistor in SOT23 envelope and designed for use as Surface Mounted Device (SMD) in thin and thick-film circuits for telephone ringer and for application with relay, high-speed and line-transformer drivers.
FEATURES • Direct interface to C-MOS, TTL, etc.
• High-speed switching • No second breakdown • Low RDS(on) Transfer admittance ID = 175 mA; VDS = 5 V PINNING - SOT23 1 2 3 PIN CONFIGURATION = gate = source = drain Yfs typ.
QUICK REFERENCE DATA Drain-source voltage Drain-source voltage (non-repetitive peak; tp ≤ 2 ms) Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source ON-resistance ID = 150 mA; VGS = 5 V RDS(on) typ.
max.
VDS VDS(SM) ±VGSO ID Ptot max.
max.
max.
max.
max.
BST82
80 V 100 V 20 V 175 mA 300 mW 7 Ω 10 Ω
150 mS
handbook, halfpage
3
handbook, 2 columns
d
g
1 Top view 2
MSB003 MBB076 - 1
s
Marking: 02p
Fig.
1 Simplified outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Drain-source voltage (non-repetitive peak; tp ≤ 2 ms) Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipation up to Tamb = 25 °C (note 1) Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient (note 1) Note 1.
Transistors mounted on a ceramic substrate of 7 mm x 5 mm x 0.
7 mm.
Rth j-a = VDS VDS(SM) ±VGSO ID IDM Ptot Tstg Tj max.
max.
max.
max.
max.
max.
max.
80 V 100 V 20 V
BST82
175 mA 600 mA 300 mW 150 °C
−65 to + 150 °C
430 K/W
April 1...
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