Document
Preliminary Datasheet
M62352P/FP/GP
8-bit 12ch D/A Converter with Buffer Amplifiers
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Description
The M62352 is an integrated circuit semiconductor of CMOS structure with 12 channels of built-in D/A converters with output buffer operational amplifiers. The 3-wire serial interface method is used for the transfer format of digital data to allow connection with microcomputer with minimum wiring. It is able to cascading serial use with DO terminal. The output buffer operational amplifier operates in the whole voltage range from power supply to ground for both input/output.
Features
12-bit serial data input (3-wire serial data transfer method) Highly stable output buffer operational amplifier allow operation in the all voltage range from power supply to
ground.
Application
Adjustment/control of industrial or home-use electronic equipment, such as VTR camera, VTR set, TV, and CRT display.
Block Diagram
GND 20
AO2
AO1
DI CLK LD
DO
AO12
AO11
VCC
19 18 17 16 15 14 13 12 11
8-bit R-2R + segment D/A converter
Ch2
8-bit latch .... (12)
D/A
1
L
12-bit shift register
D0 1 2 3 4 5 6 D7 D8 9 10 D11
(8) (12)
Address decoder
........
D/A
12
L
D/A
11
L
(12)
8-bit latch
Ch3
8-bit R-2R + segment D/A converter
L
4
D/A
L
5
D/A
L
6
D/A
L
7
D/A
L
8
D/A
L
9
D/A
L
10
D/A
++ −−
++ −−
+ −
+ −
+ −
+ −
++ −−
++ −−
Buffer OP AMP
1 2 3 4 5 6 7 8 9 10
VSS (VrefL)
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10 VDD
(VrefU)
R03DS0041EJ0400 Rev.4.00 Jun 03, 2011
Page 1 of 9
M62352P/FP/GP
Pin Arrangement
M62352P/FP/GP
VSS (VrefL) 1
20 GND
AO3 2
19 AO2
AO4 3
18 AO1
AO5 4
17 DI
AO6 5
16 CLK
AO7 6
15 LD
AO8 7
14 DO
AO9 8
13 AO12
AO10 9
12 AO11
VDD 10 (VrefU)
(Top view)
11 VCC
Outline: PRDP0020BA-A (20P4B) [P] (not recommend for new design) PRSP0020DA-A (20P2N-A) [FP] 20P2E-A [GP]
Pin Description
Pin No. 17 14 16 15 18 19 2 3 4 5 6 7 8 9 12 13 11 20 10 1
Pin Name DI DO CLK LD AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 VCC GND VDD VSS
Function Serial data input terminal Serial data output terminal Serial clock input terminal LD terminal input high level then latch circuit data load 8-bit D/A converter output terminal
Power supply terminal Digital and analog common GND D/A converter upper reference voltage input terminal D/A converter lower reference voltage input terminal
Preliminary
R03DS0041EJ0400 Rev.4.00 Jun 03, 2011
Page 2 of 9
M62352P/FP/GP
Block Diagram for Explanation of Terminals
VCC
11
DI 17 CLK 16
12-bit shift register
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Preliminary
GND
20
14 DO
(8)
D0 ..... D7 8-bit latch 8-bit R-2R D/A
+ −
+ −
Address decoder
(12)
1 2 3 4 5 6 7 8 9 10 11 12
............................... 12 ...............................
.........................................
D0 ..... D7 8-bit latch
8-bit R-2R D/A
15 LD
10 18
VDD
AO1
(VrefU)
13
AO12
1
VSS (VrefL)
Absolute Maximum Ratings
Item Supply voltage D/A converter upper reference voltag.