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SI53019-A01A

Silicon Laboratories

19-OUTPUT PCIE GEN 3 BUFFER

Si53019-A01A 19-OUTPUT PCIE GEN 3 BUFFER Features  Nineteen 0.7 V current-mode,  Spread spectrum tolerable HCSL PC...


Silicon Laboratories

SI53019-A01A

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Description
Si53019-A01A 19-OUTPUT PCIE GEN 3 BUFFER Features  Nineteen 0.7 V current-mode,  Spread spectrum tolerable HCSL PCIe Gen 3 outputs  50 ps output-to-output skew  100 MHz /133 MHz PLL operation, supports PCIe and QPI  Fixed 0 ps input to output delay  Low phase jitter (Intel QPI, PCIe Gen 1/Gen 2/Gen 3/Gen 4  PLL bandwidth SW SMBUS common clock compliant   programming overrides the latch value from HW pin 9 selectable SMBus addresses Fixed external feedback path    Gen 3 SRNS Compliant 100 ps input-to-output delay Extended Temperature: –40 to 85 °C  8 dedicated OE pin  PLL or bypass mode  Package: 72-pin QFN Ordering Information: See page 32. Applications  Server  Storage  Data Center  Network Security Description The Si53019-A01A is a 19-output, current mode HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1900Z specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/ Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Pin Assignments 72 DIF_18 71 DIF_18 70 DIF...




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