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SL23EP09 Dataheets PDF



Part Number SL23EP09
Manufacturers Silicon Laboratories
Logo Silicon Laboratories
Description Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
Datasheet SL23EP09 DatasheetSL23EP09 Datasheet (PDF)

SL23EP09  Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features • 10 to 220 MHz operating frequency range • Low output clock skew: 45ps-typ • Low output clock jitter:  50 ps-typ cycle-to-cycle jitter  20 ps-typ period jitter • Low part-to-part output skew: 90 ps-typ • Wide 2.5 V to 3.3 V power supply range • Low power dissipation:  26 mA-max at 66 MHz and VDD=3.3 V  24 mA-max at 66 MHz and VDD=2.5V • One input drives 9 outputs organized as 4+4+1 • Select mode to bypass PLL.

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SL23EP09  Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features • 10 to 220 MHz operating frequency range • Low output clock skew: 45ps-typ • Low output clock jitter:  50 ps-typ cycle-to-cycle jitter  20 ps-typ period jitter • Low part-to-part output skew: 90 ps-typ • Wide 2.5 V to 3.3 V power supply range • Low power dissipation:  26 mA-max at 66 MHz and VDD=3.3 V  24 mA-max at 66 MHz and VDD=2.5V • One input drives 9 outputs organized as 4+4+1 • Select mode to bypass PLL or tri-state outputs • SpreadThru™ PLL that allows use of SSCG • Standard and High-Drive options • Available in 16-pin SOIC and TSSOP packages • Available in Commercial and Industrial grades Applications • Printers, MFPs and Digital Copiers • PCs and Work Stations • Routers, Switchers and Servers • Digital Embeded Systems Block Diagram Description The SL23EP09 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL23EP09 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tri-stated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The high-drive version operates up to 220MHz and 200MHz at 3.3V and 2.5V power supplies respectively. Benefits • Up to nine (9) distribution of input clock • Standard and High-Dirive levels to control impedance level, frequency range and EMI • Low power dissipation, jitter and skew • Low cost CLKIN Low Power and Low Jitter PLL MUX S2 Input Selection Decoding Logic S1 2 VDD 2 GND CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Rev 2.0, May 12, 2008 2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 Page 1 of 14 www.silabs.com SL23EP09 Pin Configuration CLKIN CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 CLKOUT 15 CLKA4 14 CLKA3 13 VDD 12 GND 11 CLKB4 10 CLKB3 9 S1 16-Pin SOIC and TSSOP Pin Description Pin Pin Name Number 1 CLKIN 2 CLKA1 3 CLKA2 4 VDD 5 GND 6 CLKB1 7 CLKB2 8 S2 9 S1 10 CLKB3 11 CLKB4 12 GND 13 VDD 14 CLKA3 15 CLKA4 16 CLKOUT Pin Type Pin Description Input Output Output Power Power Output Output Input Input Output Output Power Power Output Output Output Reference Frequency Clock Input. Weak pull-down (250kΩ). Buffered Clock Output, Bank A. Weak pull-down (250kΩ). Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 3.3V or 2.5V Power Supply. Power Ground. Buffered Clock Output, Bank B. Weak pull-down (250kΩ). Buffered Clock Output, Bank B. W.


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