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D5NM50 Dataheets PDF



Part Number D5NM50
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description STD5NM50
Datasheet D5NM50 DatasheetD5NM50 Datasheet (PDF)

STD5NM50 STD5NM50-1 N-CHANNEL 500V - 0.7Ω - 7.5A DPAK/IPAK MDmesh™Power MOSFET TYPE VDSS RDS(on) ID STD5NM50 STD5NM50-1 500V 500V <0.8Ω <0.8Ω 7.5 A 7.5 A n TYPICAL RDS(on) = 0.7Ω n HIGH dv/dt AND AVALANCHE CAPABILITIES n 100% AVALANCHE TESTED n LOW INPUT CAPACITANCE AND GATE CHARGE n LOW GATE INPUT RESISTANCE n TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’.

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STD5NM50 STD5NM50-1 N-CHANNEL 500V - 0.7Ω - 7.5A DPAK/IPAK MDmesh™Power MOSFET TYPE VDSS RDS(on) ID STD5NM50 STD5NM50-1 500V 500V <0.8Ω <0.8Ω 7.5 A 7.5 A n TYPICAL RDS(on) = 0.7Ω n HIGH dv/dt AND AVALANCHE CAPABILITIES n 100% AVALANCHE TESTED n LOW INPUT CAPACITANCE AND GATE CHARGE n LOW GATE INPUT RESISTANCE n TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. 3 1 DPAK TO-252 3 2 1 IPAK TO-251 (Add Suffix “-1”) INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDS VDGR VGS Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage ID Drain Current (continuous) at TC = 25°C ID Drain Current (continuous) at TC = 100°C IDM (l) Drain Current (pulsed) PTOT Total Dissipation at TC = 25°C Derating Factor dv/dt (1) Peak Diode Recovery voltage slope Tstg Storage Temperature Tj Max. Operating Junction Temperature (•)Pulse width limited by safe operating area September 2002 Value 500 500 ±30 7.5 4.7 30 100 0.8 15 Unit V V V A A A W W/°C V/ns – 55 to 150 °C (1) ISD ≤ 5A, di/dt ≤ 400A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. 1/10 STD5NM50/STD5NM50-1 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max Tl Maximum Lead Temperature For Soldering Purpose 1.25 100 300 AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value 2.5 300 ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Min. Typ. Max. V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 500 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 1 10 IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 °C/W °C/W °C Unit A mJ Unit V µA µA nA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250µA VGS = 10V, ID = 2.5A Min. 3 Typ. 4 0.7 Max. 5 0.8 Unit V Ω DYNAMIC Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance VDS = 25Vx, ID = 2.5A 3.5 S Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 415 pF Coss Output Capacitance 88 pF Crss Reverse Transfer Capacitance 12 pF Coss eq. (2) Equivalent Output Capacitance VGS = 0V, VDS = 0V to 400V 50 pF RG Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 3Ω 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 2/10 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol Parameter Test Conditions td(on) tr Turn-on Delay Time Rise Time VDD = 250V, ID = 2.5A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) Qg Total Gate Charge Qgs Gate-Source Charge VDD = 400V, ID = 7.5A VGS = 10V Qgd Gate-Drain Charge SWITCHING OFF Symbol Parameter tr(Voff) Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions VDD = 400V, ID = 5A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) STD5NM50/STD5NM50-1 Min. Typ. 16 8 13 5 6 Max. Unit ns ns nC nC nC Min. Typ. 14 6 13 Max. Unit ns ns ns SOURCE DRAIN DIODE Symbol Parameter Test Conditions Min. ISD Source-drain Current ISDM (2) Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 7.5A, VGS = 0 trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 5A, di/dt = 100A/µs, VDD = 100V, Tj = 25°C (see test circuit, Figure 5) trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 5A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance Typ. 185 1.1 11.5 270 1.6 12 Max. 7.5 30 1.5 Unit A A V ns µC A ns µC A 3/10 STD5NM50/STD5NM50-1 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/10 Normalized Gate Threshold Voltage vs Temperature STD5NM50/STD5NM50-1 Normalized On Re.


C4398 D5NM50 KBL405G


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