Document
ESMT
Flash
FEATURES
Single supply voltage 2.7~3.6V Standard, Dual and Quad SPI Speed
- Read max frequency: 33MHz - Fast Read max frequency: 50MHz / 86MHz / 100MHz - Fast Read Dual/Quad max frequency: 50MHz / 86MHz / 100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI; 200MHz / 344MHz / 400MHz equivalent Quad SPI)
Low power consumption - Active current: 25 mA (max.) - Standby current: 25 μ A (max.) - Deep Power Down current: 10 μ A (max.)
Reliability - 100,000 typical program/erase cycles - 20 years Data Retention
Program - Page programming time: 1.5 ms (typical)
F25L08QA (2S)
8 Mbit Serial Flash Memory with Dual and Quad
Erase - Chip Erase time 7 sec (typical) - 64K bytes Block Erase time 0.75 sec (typical) - 32K bytes Block Erase time 500 ms (typical) - 4K bytes Sector Erase time 90 ms (typical)
Page Programming - 256 byte per programmable page
Lockable 512 bytes OTP security sector SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3 End of program or erase detection
Write Protect ( WP )
Hold Pin ( HOLD ) All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
Speed
F25L08QA –50PG2S F25L08QA –86PG2S F25L08QA –100PG2S F25L08QA –50PAG2S F25L08QA –86PAG2S F25L08QA –100PAG2S F25L08QA –50HG2S F25L08QA –86HG2S F25L08QA –100HG2S
50MHz 86MHz 100MHz 50MHz 86MHz 100MHz 50MHz 86MHz 100MHz
Package
Comments
8-lead SOIC
150 mil
Pb-free
8-lead SOIC
200 mil
Pb-free
8-contact WSON
6x5 mm
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
1/43
ESMT
F25L08QA (2S)
GENERAL DESCRIPTION
The F25L08QA is a 8Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles.
The memory array can be organized into 4,096 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction.
The device features sector erase architecture. The memory array
is divided into 256 uniform sectors with 4K byte each; 32 uniform blocks with 32K byte each; 16 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase.
The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory.
FUNCTIONAL BLOCK DIAGRAM
Page Address Latch / Counter
High Voltage Generator
Status Register
Byte Address Latch / Counter
Memory Array
Page Buffer
Y-Decoder
Command and Conrol Logic Serial Interface
CE SCK
SI
SO WP HOLD
(SIO0) (SIO1) (SIO2) (SIO3)
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
2/43
ESMT
PIN CONFIGURATIONS
8-Lead SOIC (SOIC 8L, 150mil Body, 1.27mm Pin Pitch) (SOIC 8L, 208mil Body, 1.27mm Pin Pitch)
CE SO / SIO1 WP / SIO2
VSS
1 2 3 4
F25L08QA (2S)
8 VDD 7 HOLD / SIO3 6 SCK 5 SI / SIO0
8- Contact WSON (WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch)
CE SO WP VSS
1 2 3 4
8 7 6 5
VDD HOLD SCK SI
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
3/43
ESMT
F25L08QA (2S)
PIN DESCRIPTION
Symbol SCK
SI / SIO0
Pin Name Serial Clock
Serial Data Input / Serial Data Input Output 0
SO / SIO1
Serial Data Output / Serial Data Input Output 1
CE WP / SIO2
Chip Enable
Write Protect / Serial Data Input Output 2
Hold / HOLD / SIO3 Serial Data Input Output 3
VDD Power Supply VSS Ground
Functions
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK(for Dual/Quad mode).
To transfer data serially out of the device. Data is shifted out on the falling edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Dual/Quad mode).
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Quad mode).
To temporality stop serial communication with SPI flash memory without resetting the device. / Bidirectional IO pin to transfer commands, addresses or data serially into the devic.