Document
OptiMOS™-T2 Power-Transistor
Features • N-channel - Enhancement mode • AEC Q101 qualified • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green Product (RoHS compliant) • 100% Avalanche tested
IPD50N08S4-13
Product Summary VDS RDS(on),max ID
80 V 13.2 mW 50 A
PG-TO252-3-313
Type IPD50N08S4-13
Package
Marking
PG-TO252-3-313 4N0813
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol
Conditions
Continuous drain current1)
I D T C=25°C, V GS=10V
T C=100°C, V GS=10V2)
Pulsed drain current2) Avalanche energy, single pulse2) Avalanche current, single pulse Gate source voltage Power dissipation Operating and storage temperature
I D,pulse T C=25°C
E AS I D=25A
I AS -
V GS
-
P tot T C=25°C
T j, T stg -
Value 50
50
200 76 31 ±20 72 -55 ... +175
Unit A
mJ A V W °C
Rev. 1.0
page 1
2014-06-30
IPD50N08S4-13
Parameter
Symbol
Conditions
Thermal characteristics2)
Thermal resistance, junction - case SMD version, device on PCB
R thJC R thJA
minimal footprint 6 cm2 cooling area3)
min.
Values typ.
Unit max.
- - 2.1 K/W - - 62 - - 40
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current
Gate-source leakage current Drain-source on-state resistance
V (BR)DSS V GS=0V, I D= 1mA V GS(th) V DS=V GS, I D=33µA
I DSS
V DS=80V, V GS=0V, T j=25°C
V DS=80V, V GS=0V, T j=125°C2)
I GSS
V GS=20V, V DS=0V
R DS(on) V GS=10V, I D=50A
80 -
-V
2.0 3.0 4.0
- 0.01 1 µA
- 5 100
- - 100 nA - 11.2 13.2 mW
Rev. 1.0
page 2
2014-06-30
IPD50N08S4-13
Parameter
Dynamic characteristics2) Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time
Gate Charge Characteristics2) Gate to source charge Gate to drain charge Gate charge total Gate plateau voltage
Reverse Diode Diode continous forward current2) Diode pulse current1)
Diode forward voltage
Reverse recovery time1)
Symbol
Conditions
C iss C oss Crss t d(on) tr t d(off) tf
V GS=0V, V DS=25V, f =1MHz
V DD=40V, V GS=10V, I D=50A, R G=3.5W
Q gs
Q gd V DD=64V, I D=50A, Q g V GS=0 to 10V
V plateau
IS I S,pulse
T C=25°C
V SD
V GS=0V, I F=50A, T j=25°C
t rr
V R=50V, I F=I S, di F/dt =100A/µs
min.
Values typ.
Unit max.
- 1316 1711 pF - 511 664 - 29 58 - 5.0 - ns - 3.6 - 6.4 - 11.8 -
- 6.9 9.0 nC - 4.5 9 - 19 30 - 5.0 - V
- - 50 A - - 200 - 0.9 1.3 V
- 74 - ns
Reverse recovery charge1)
Q rr
- 49 - nC
1) Current is limited by bondwire; with an R thJC = 2.1K/W the chip is able to carry 85A at 25°C.
2) Specified by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air.
Rev. 1.0
page 3
2014-06-30
IPD50N08S4-13
1 Power dissipation P tot = f(T C); V GS ≥ 6 V
2 Drain current I D = f(T C); V GS = 10 V
Ptot [W] ID [A]
80
70.