1:1 Differential-to-LVDS Zero Delay Clock Generator
1:1 Differential-to-LVDS Zero Delay Clock Generator
ICS8745BI-21
DATA SHEET
General Description
Features
The ICS874...
Description
1:1 Differential-to-LVDS Zero Delay Clock Generator
ICS8745BI-21
DATA SHEET
General Description
Features
The ICS8745BI-21 is a highly versatile 1:1 LVDS Clock Generator. The ICS8745BI-21 has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clock. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
Pin Assignments
CLK nCLK
MR nFB_IN
FB_IN SEL2 VDDO nQFB
QFB GND
1 2
3 4 5 6 7 8
9 10
20 SEL1 19 SEL0
18 VDD 17 PLL_SEL
16 VDDA 15 SEL3 14 GND 13 Q
12 nQ 11 VDDO
ICS8745BI-21
One differential LVDS output designed to meet
or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair
Differential CLK, nCLK input pair CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz Input frequency range: 31.25MHz to 700MHz VCO range: 250MHz to 700MHz External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable divi...
Similar Datasheet