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NCP81111
3 Phase VR12.56 High Speed Digital Controller with SVID and I2C Interfaces for 5 MHz Desktop, Notebook CPU Applications
The NCP81111 is a high performance digital single output three phase VR12.5−6 compatible buck solution optimized to operate at frequencies up to 5 MHz for Intel CPU applications. The NCP81111 and can also work as a general purpose I2C controlled multiphase voltage regulator. The NCP81111 is designed to support the NCP81163 digital phase doubler IC which expands the capability of the part to 6 phases for high current handling. The controller includes true differential voltage sensing, differential current sensing, digital input voltage feed−forward, DAC feed forward, and adaptive voltage positioning. These features combine to provide an accurately regulated dynamic voltage system. The control system makes use of digital constant on time modulation and is combined with an analog and digital current sensing system. This system provides the fastest initial response to dynamic load events to reduced system cost. On board user programmable memory is included for configuring the controller’s parameters. User programmable voltage and droop compensation is internally integrated to minimize the total board space used. The NCP81111 is optimized for use with DRMOS.
Features
• Meets Intel®’s VR12.5 Specifications • On Board EEPROM for User Configuration • High Performance Digital Architecture • Dynamic Reference Injection • Fully Differential Voltage Current Sense Amplifiers • “Lossless” DCR Current Sensing for Current Balancing • Thermally Compensated Inductor Current Sensing for Droop • User Adjustable Internal Compensation • Switching Frequency Range of 250 kHz − 5.0 MHz • Input Voltage Feed−forward • Startup into Pre−Charged Loads • Power Saving Phase Shedding • Supports Lower Power Operation in PS3 • This is a Pb−Free Device
Applications
• Desktop, Notebook Processors, and General Purpose I2C Controlled
Multiphase Regulators.
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MARKING DIAGRAM
1 32
QFN32 CASE 485CE
1
NCP81111 zzRr
AWLYYWWG G
NCP81111 = Specific Device Code zz = Configuration Option Rr = Revision Number A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device*
Package Shipping†
NCP81111MNDFTXG QFN32 2500 / Tape &
(Pb−Free)
Reel
NCP81111MNzzTXG QFN32 2500 / Tape &
(Pb−Free)
Reel
*zz = Configurable Option, please contact Sales for additional information.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 4
1
Publication Order Number: NCP81111/D
NCP81111
SDIO ALERT# SCLK VR_RDY VR_HOT# T_SENSE VSN VSP
32 31 30 29 28 27 26 25
SDA 1 SCL 2
EN 3 TEST3/I2CADDR0 4
VFF 5 VDIG 6 VCCD 7 VCCA 8
GND
24 TEST1 23 TEST2/I2CADDR1 22 CSP1 21 CSN1 20 CSP2 19 CSN2 18 CSP3 17 CSN3
9 10 11 12 13 14 15 16
VCCP PWM1 SMOD1 DRVON PWM2 SMOD2 PWM3 SMOD3
Figure 1. Pinout Diagram
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NCP81111
VID<> OV_THRESHOLD<>
3V
DAC OV_TRSHLD
AGND DUAL DAC
VCCA VDIG
UVLO
VSP OV_TRSHLD OVP VSN OVP COMPARATOR
COMPENSATION SETTINGS<>
DIFFOUT
UVLO
SDA
SETTINGS
SCL
EN DRVON
SCLK
ALERT#
VR_RDY
SDIO
VRHOT#
FAULT STATUS
ANALOG MONITORING
Nonvolatile Memory
DIGITAL INTERFACE
DIFFOUT 0.85V UVP MONITOR
+ CSP1 − CSN1 + CSP2 − CSN2 + CSP3 − CSN3
CSP CSN
CSP
Av
CSN GAIN<>
DROOP_P DROOP_N
DROOP CURRENT SUMMING AMP
DROOP GAIN CONTROL
5us Blanking UVP
+ V1P3 − DAC + VSP − VSN DIFFOUT + GND + DROOP_P − DROOP_N
SUMMING AMP
CSP1 CSN1
TEMP_CONTROL<> CSP
CSN THERMAL COMPENSATION
V1 1.3Vdc
0
HIGH SPEED PROGRAMMABLE COMPENSATOR
DIFFOUT V1P3
DIGITAL INTEGRATOR
Ioffset
100MHz VN
COMP VP ERROR AMP
CSP2 CSN2
TEMP_CONTROL<> CSP
CSN THERMAL COMPENSATION
CSP3
TEMP_CONTROL<> CSP
CSN3
CSN
THERMAL COMPENSATION
PHASE MUX
+ CSP1 − CSN1 + CSP2 − CSN2 + CSP3 − CSN3
CSP CSN
VFF AtoD VFF_OUT<>
VFF MONITOR
+ CSP1 − CSN1 + CSP2 − CSN2 + CSP3 − CSN3
CSP CSN
CURRENT LIMIT CURRENT SUMMING AMP
CURRENT LIMIT CURRENT LIMIT<>
DAC
CSP CSN
ZCD_THRESHOLD<> DAC
CSP1 CSN1
ZCD COMPARE
ZDC1
6BIT FLASH CSP
CSOUT<5:0>
CSN
OCP
TRIGGER PWM_GO1
PSx STATE PWM_GO2
FAULTS
PWM_GO3
RAMP_GO
PHASE COUNT<>
SMOD1
ZCD1
SMOD2
SMOD3
PWM CONTROL
FREQ SETTING TON1<>
PSx STATE TON2<>
CSOUT TON3<>
VFF_OUT<>
TON CONTROL
+ CSP1 − CSN1 + CSP2 − CSN2 + CSP3 − CSN3
CSP CSN
IOUT CURRENT SUMMING AMP
IOUT GAIN CONTROL
CSP
Av
IOUT_P
CSN
IOUT_N
GAIN<>
PHASE MUX
+VSP − VSN +T_SENSE −T_SENSE IOUT_P IOUT_N
AOUT_P AOUT_N
IN_P IN_N
10BIT AtoD OUT<9:0>
Figure 2. Block Diagram
GAIN<> STOP VFB COMP
V_THRESHOLD<>
DAC COMP
+ − STOP
STOP CONTROL
Ramp Current<> Ramp Cap<> Ramp Reset Voltage <> Phase Count<>
RAMP_GO
RAMP GENERATOR
RAMP
5ns
RAMP TRIGGER
COMP
RAMP COMPARATOR
PWM_GO TON<10:0> PWM CLK_800MHZ Ton Timer
PWM_GO TON<10:0> P.