A48P4616B

Document Title 16M X 16 Bit DDR DRAM Revision History Rev. No. History 1.0 Initial issue A48P4616B 16M X 16 Bit DDR DRAM Issue Date January 9, 2014 Remark Final (January, 2014, Version 1.0) AMIC Technology, Corp. A48P4616B 16M X 16 Bit DDR DRAM Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 (5) 133 166 200 „ Double data rate architecture: two data transfers per clock cycle. „ Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver. „ DQS is edge-aligned with data for reads and is centeraligned with data for writes. „ Differential clock inputs (CK and CK ) „ Four internal banks for concurrent operation. „ Data mask (DM) for write data. „ DLL aligns DQ and DQS transitions with CK transitions. „ Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS. „ Burst lengths: 2, 4, or 8 „ CAS Latency: 2/2.5/3 „ Auto Precharge option for each burst access „ Auto Refresh and Self Refresh Modes „ 8192 refresh cycles / 64ms (4 banks concurrent refresh) „ 2.5V (SSTL_2 compatible) I/O „ VDD = VDDQ = 2.5V ± 0.2V „ Industrial operating temperature range: -40ºC to +85ºC for -U series. „ Available Lead Free packaging „ All Pb-free (Lead-free) products are RoHS compliant General Description The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch...