Document
54AC 74AC16954ACT 74ACT169 4-Stage Synchronous Bidirectional Counter
April 1993
54AC 74AC16954ACT 74ACT169
4-Stage Synchronous Bidirectional Counter
General Description
The ’AC ’ACT169 is fully synchronous 4-stage up down counter The ’AC ’ACT169 is a modulo-16 binary counter It features a preset capability for programmable operation carry lookahead for easy cascading and a U D input to control the direction of counting All state changes whether in counting or parallel loading are initiated by the LOW-toHIGH transition of the Clock
Features
Y ICC reduced by 50% Y Synchronous counting and loading Y Built-In lookahead carry capability Y Presettable for programmable operation Y Outputs source sink 24 mA Y ’ACT has TTL-compatible inputs Y Standard Military Drawing (SMD)
’AC169 5962-91603
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment for DIP Flatpak and SOIC
TL F 9934–1
Pin Names
CEP CET CP P0 – P3 PE UD Q0 – Q3 TC
Description
Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Parallel Data Inputs Parallel Enable Input Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output
FACTTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9934
TL F 9934 – 2
TL F 9934 – 3
Pin Assignment for LCC
TL F 9934 – 4 RRD-B30M75 Printed in U S A
Logic Diagram
TL F 9934 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
Functional Description
The ’AC ’ACT169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the Clock The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter The parallel load operation takes precedence over the other operations as indicated in the Mode Select Table When PE is LOW the data on the P0 – P3 inputs enters the flip-flops on the next rising edge of the Clock In order for counting to occur both CEP and CET must be LOW and PE must be HIGH the U D input then determines the direction of counting The Terminal Count (TC) output is normally HIGH and goes LOW provided that CET is LOW when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode The TC output state is not a function of the Count Enable Parallel (CEP) input level If an illegal state occurs the ’AC169 will return to the legitimate sequence within two counts Since the TC signal is derived by decoding the flip-flop states there exists the possibility of decoding spikes on TC For this reason the use of TC as a clock signal is not recommended (see logic equations below)
1) Count Enable e CEPCETPE
2) Up TC e Q0Q1Q2Q3(Up)CET 3) Down TC e Q0Q1Q2Q3(Down)CET
Mode Select Table
PE CEP CET U D
Action on Rising Clock Edge
L X X X Load (Pn to Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold)
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial
State Diagrams
TL F 9934 – 6
2
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications
Supply Voltage (VCC)
DC Input Diode Current (IIK) VI e b0 5V VI e VCC a 0 5V
DC Input Voltage (VI)
DC Output Diode Current (IOK) VO e b0 5V VO e VCC a 0 5V
DC Output Voltage (VO)
DC Output Source or Sink Current (IO)
DC VCC or Ground Current per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ) CDIP PDIP
b0 5V to a7 0V
b20 mA a20 mA b0 5V to VCC a 0 5V
b20 mA a20 mA b0 5V to VCC a 0 5V
g50 mA
g50 mA b65 C to a150 C
175 C 140 C
Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation of FACTTM circuits outside databook specifications
Recommended Operating
Conditions
Supply Voltage (VCC) ’AC
’ACT
2 0V to 6 0V 4 5V to 5 5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA) 74AC ACT 54AC ACT
0V to VCC 0V to VCC
b40 C to a85 C b55 C to a125 C
Minimum Input Edge Rate (DV Dt) ’AC Devices VIN from 30% to 70% of VCC VCC 3 3V 4 5V 5 5V
Minimum Input Edge Rate (DV Dt) ’ACT Devices VIN from 0 8V to 2 0V VCC 4 5V 5 5V
125 mV ns 125 mV ns
DC Characteristics for ’AC Family Devices
Symbol
Parameter
VCC (V)
VIH Minimum High Level 3 0
Input Voltage
45
55
VIL Maximum Low Level 3 0
Input Voltage
45
55
VOH Minimum High Level 3 0
Output Voltage
45
55
74AC
TA e a25 C
Typ
15 2 25 2 75
15 2 25 2 75
2 99 4 49 5 49
21 3 15 3 85
09 1 35 1 65
29 44 54
54AC
74AC
TA e
TA e
b55 C to a125 C b40 .