Document
CEP840L/CEB840L
CEF840L
N-Channel Enhancement Mode Field Effect Transistor
PRELIMINARY
FEATURES
Type CEP840L CEB840L
VDSS 500V 500V
CEF840L
500V
RDS(ON) 0.8Ω 0.8Ω 0.8Ω
ID @VGS 8A 10V 8A 10V 8A e 10V
Super high dense cell design for extremely low RDS(ON).
High power and current handing capability. Lead free product is acquired.
D
G
D
G S
CEB SERIES TO-263(DD-PAK)
G D S
CEP SERIES TO-220
G
D S CEF SERIES
TO-220F
S
ABSOLUTE MAXIMUM RATINGS Tc = 25 C unless otherwise noted
Parameter
Symbol
Limit
TO-220/263
TO-220F
Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Maximum Power Dissipation @ TC = 25 C
- Derate above 25 C
VDS 500
VGS ±20
ID 8 8 e
IDM f
32 32 e
125 40 PD 1.0 0.32
Operating and Store Temperature Range
TJ,Tstg
-55 to 150
Thermal Characteristics
Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient
Symbol RθJC RθJA
Limit 1.0 62.5
3.1 65
Units
V V A A W W/ C C
Units C/W C/W
This is preliminary information on a new product in development now . Details are subject to change without notice .
1
Rev 1. 2007.Nov. http://www.cet-mos.com
CEP840L/CEB840L CEF840L
Electrical Characteristics Tc = 25 C unless otherwise noted
Parameter
Symbol
Test Condition
Off Characteristics
Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b
BVDSS IDSS IGSSF IGSSR
VGS = 0V, ID = 250µA VDS = 500V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V
Gate Threshold Voltage Static Drain-Source On-Resistance
VGS(th) RDS(on)
VGS = VDS, ID = 250µA VGS = 10V, ID = 4.8A
Forward Transconductance Dynamic Characteristics c
gFS VDS = 50V, ID = 4.8A
Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c
Ciss Coss Crss
VDS = 25V, VGS = 0V, f = 1.0 MHz
Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time
td(on) tr
td(off)
VDD = 250V, ID = 8A, VGS = 10V, RGEN = 9.1Ω
Turn-Off Fall Time
tf
Total Gate Charge Gate-Source Charge Gate-Drain Charge
Qg Qgs
VDS = 400V, ID = 8A, VGS = 10V
Qgd
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b
IS f VSD
VGS = 0V, IS = 8A
Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature . b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% . c.Guaranteed by design, not subject to production testing. d.Limited only by maximum temperature allowed . e.Pulse width limited by safe operating area . f.Full package IS(max) = 4.6A .
Min 500
1
Typ
0.6 7 1240 145 20 20 9 48 8 33 6.2 13.9
Max Units
25 100 -100
V µA nA nA
3V 0.8 Ω
S
pF pF pF
40 ns 18 ns 92 ns 16 ns 43.8 nC
nC nC
8A 1.5 V
2
ID, Drain Current (A)
C, Capacitance (pF)
12 VGS=10,9,8,7V
10
8 VGS=6V
6
4 VGS=5V
2
0 0 2 4 6 8 10 12
VDS, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
CEP840L/CEB840L CEF840L
ID, Drain Current (A)
18
15
12
9
6 25 C
3 TJ=125C
-55 C
0 123456
VGS, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
1800
1500 1200
Ciss
900
600 300 Coss
0 Crss 0 5 10 15 20 25
VDS, Drain-to-Source Voltage (V)
Figure 3. Capacitance
1.3 VDS=VGS 1.2 ID=250µA
1.1
1.0
0.9
0.8
0.7
0.6 -50 -25 0 25 50 75 100 125 150
TJ, Junction Temperature( C)
Figure 5. Gate Threshold Variation with Temperature
RDS(ON), Normalized RDS(ON), On-Resistance(Ohms)
IS, Source-drain current (A)
2.2 ID=4.8A 1.9 VGS=10V 1.6 1.3 1.0 0.7 0.4
-100 -50 0 50 100 150 200
TJ, Junction Temperature( C) Figure 4. On-Resistance Variation
with Temperature
100 VGS=0V
10-1
10-2 0.4 0.6 0.8 1.0 1.2
VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage
Variation with Source Current
VTH, Normalized Gate-Source Threshold Voltage
3
VGS, Gate to Source Voltage (V) ID, Drain Current (A)
10 VDS=400V ID=8A
8
6
4
2
0 0 10 20 30 40 50
Qg, Total Gate Charge (nC) Figure 7. Gate Charge
VDD
VIN RL D VOUT
VGS RGEN G
S
CEP840L/CEB840L CEF840L
RDS(ON)Limit
100ms 101 1ms
10ms DC 100
TC=25 C TJ=150 C Single Pulse 10-1 100 101 102 103
VDS, Drain-Source Voltage (V)
Figure 8. Maximum Safe Operating Area
td(on) VOUT
t on tr
td(off)
90%
10% INVERTED
toff tf
90%
10%
VIN
10%
50%
90% 50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
r(t),Normalized Effective Transient Thermal Impedance
100 D=0.5
10-1 10-2
0.2 0.1
0.05 0.02 0.01
Single Pulse
10-3 10-5
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (sec)
PDM
t1 t2
1. R JC (t)=r (t) * R JC 2. R JC=See Datasheet 3. TJM-TC = P* R JC (t) 4. Duty Cycle, D=t1/t2
100
101
Figure 11. Normalized Thermal Transient Impedance Curve
4
.