Document
NB3N51044
3.3 V, Crystal to 100 MHz / 125 MHz Quad HCSL / LVDS Clock Generator
The NB3N51044 is a precision, low phase noise clock generator that supports PCI Express and sRIO clock requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz single ended reference clock signal and generates four differential HCSL/LVDS outputs (See Figure 10 for LVDS interface) of 100 MHz or 125 MHz clock frequency based on frequency select input F_SEL. NB3N51044 is configurable to bypass the PLL from signal path using BYPASS, and provides the output frequency through the divider network. All clock outputs can be individually enabled / disabled through hardware input pins OE[3:0]. In addition, device can be reset using Master Reset input pin MR_OE#.
Features
• Uses 25 MHz Fundamental Crystal or Reference Clock Input • Four Low Skew HCSL or LVDS Outputs • Output Frequency Selection of 100 MHz or 125 MHz • Individual OE Tri−States Outputs • Master Reset and BYPASS Modes • PCIe Gen 1, Gen 2, Gen 3 Compliant • Typical Phase Jitter @ 125 MHz (Integrated 1.875 MHz to 20 MHz):
0.2 ps
• Typical Cycle−Cycle Jitter @ 100 MHz (10k cycles): 20 ps • Phase Noise @ 100 MHz:
Offset Noise Power 100 Hz −101 dBc/Hz 1 kHz −123 dBc/Hz 10 kHz −133 dBc/Hz 100 kHz −136 dBc/Hz 1 MHz −141 dBc/Hz 10 MHz −155 dBc/Hz
• Operating Supply Voltage Range 3.3 V ±5% • Industrial Temperature Range −40°C to +85°C • Functionally Compatible with ICS841604I with enhanced performance • These are Pb−Free Devices
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MARKING DIAGRAM
TSSOP−28 DT SUFFIX CASE 948AA
NB3N5 1044G ALYW
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.
Applications
• Networking • Consumer • Computing and Peripherals • Industrial Equipment • PCIe Clock Generation Gen 1, Gen 2 and Gen 3
End Products
• Switch and Router • Set Top Box, LCD TV • Servers, Desktop Computers • Automated Test Equipment
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 1
1
Publication Order Number: NB3N51044/D
VDD
XIN
25 MHz Crystal
XOUT
REF_IN
Clock Buffer/ Cystal Oscillator
GND REF_SEL
NB3N51044
BLOCK DIAGRAM
BYPASS MR_OE#
HCSL buffer
Phase Detector
Charge Pump
VCO
Feedback Divider
0 Output
1 Divider ($N)
Figure 1. Block Diagram PIN CONFIGURATION
F_SEL
HCSL buffer
HCSL buffer
HCSL buffer
IREF
REF_SEL REF_IN VDD GND XIN XOUT
MR_OE# VDD OE3 OE2 OE1 OE0 GND VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
NB3N51044
28 VDD 27 BYPASS 26 IREF 25 F_SEL 24 VDD 23 CLK3 22 CLK3 21 CLK2 20 CLK2 19 GND 18 CLK1 17 CLK1 16 CLK0 15 CLK0
Figure 2. Pin Configuration (Top View)
CLK3 CLK3 OE3 CLK2 CLK2
OE2 CLK1 CLK1
OE1 CLK0 CLK0
OE0
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NB3N51044
PIN DESCRIPTION
Table 1. PIN DESCRIPTION
Pin # Pin Name
Type
Description
1 REF_SEL
Input
LVCMOS/ LVTTL level input to select input reference source. Pulldown with crystal as default reference input source.
2 REF_IN
Input
25 MHz single−ended reference input clock.
3 VDD 4 GND
Power Ground
Positive supply voltage pin connected to +3.3 V typical supply voltage. Power supply ground 0 V. This pin provides GND return path for the device.
5 XIN
Input
25 MHz fundamental mode crystal input connection. Ground this pin when crystal not connected.
6 XOUT
Output 25 MHz crystal output. Float this pin when crystal not connected.
7 MR_OE#
Input
Asynchronous LVCMOS/ LVTTL level input. When High, this pin acts as Master Reset to disable the output dividers and set outputs to high impedance (Hi−Z) mode. When Low, this pin acts as Output Enable for enabling the output buffers. Pulldown with default Low.
8 VDD 9 OE3
Power Input
Positive supply voltage pin connected to +3.3 V typical supply voltage.
LVCMOS/ LVTTL level interface active High output enable pin for CLK3. Pulldown with default Low and output disabled.
10 OE2
Input
LVCMOS/ LVTTL level interface active High output enable pin for CLK2. Pulldown with default Low and output disabled.
11 OE1
Input
LVCMOS/ LVTTL level interface active High output enable pin for CLK1. Pulldown with default Low and output disabled.
12 OE0
Input
LVCMOS/ LVTTL level interface active High output enable pin for CLK0. Pulldown with default Low and output disabled.
13 GND
Ground Power supply ground 0 V. This pin provides GND return path for the device.
14 VDD
Power
Positive supply voltage pin connected to +3.3 V typical supply voltage.
15
CLK0
HCSL or LVDS output
Noninverted clock output. (For LVDS levels see Figure 10)
16
CLK0
HCSL or LVDS output
Inverted clock output. (For LVDS levels see Figure 10)
17
CLK1
HCSL or LVDS output
Noninverted clock output. (For LVDS levels see Figure 10)
18
CLK1
HCSL or LVDS output
Inverted clock output. (For LVDS levels see Figure 10)
19 GND
Ground Power supply ground 0 V. This pin provides GND return path for the device.
20
CLK2.