Document
SH79F085/SH79F165
Enhanced 8051 Microcontroller with 20-Bit ADC
1. Features
� 8051 compatible Pipe-lined instruction based on the single-chip 8-bit microcontroller
� Flash ROM: - SH79F085: 8K Bytes - SH79F165: 16K Bytes
� RAM: internal 256 Bytes, external 256 Bytes
� EEPROM: internal 512 Bytes
� Operation Voltage: VDD = 3.0V - 5.5V � Oscillator (code option):
- Crystal oscillator: 400kHz - 16.6MHz - Crystal oscillator: 32.768kHz - Internal RC: 16.6MHz - Internal RC: 128kHz � 15/19 CMOS bi-directional I/O pins - SH79F085: 15/19 I/O - SH79F165: 19 I/O
� Built-in pull-up resistor for input pin
� Four 16-bit timer/counters: T0, T1, T2, T3 � Built-in EUART
� Powerful interrupt sources: - Timer0, Timer1, Timer2, Timer3 - INT0 - 2 - ADC, EUART, SCM
� Built-in Buzzer
� In system programming (ISP)
� Built-in regulator - Output voltage: 2.7V
� 20-Bit Σ-ΔAnalog Digital Converter (ADC) - 20-bit data output, 16-bit resolution - SH79F085: 2 differential input - SH79F165: 3 differential input
� Built-in Programmable Gain Amplifier (PGA) - Gain: 12.5X - 200X
� Built-in Low Voltage Reset (LVR) function - LVR Voltage: 3.1V - LVR Voltage: 4.3V
� CPU Machine cycle: 1 oscillator clock � Built-in Watch Dog Timer (WDT) (code option)
� Built-in oscillator Warm-up Timer
� Support low power operation modes: - IDLE Mode - Power-Down Mode
� Flash Type
� Package: - SH79F085: TSSOP20/SOP24 - SH79F165: SOP24
2. General Description
The SH79F085/SH79F165 is a fast 8051 compatible micro-controller with a redesigned CPU of no wasted clock and memory cycles. Typically, it will be faster and exhibit better performance than the traditional 8051 at the same oscillator frequency.
The SH79F085/SH79F165 retains most features of the standard 8051. These features include internal 256 bytes RAM and four 16-bit timer/counters, one UART, and external interrupt INT0, INT1 & INT2. The SH79F085 contains 8K bytes Flash memory block both for program and data. The SH79F165 contains 16K bytes Flash memory block both for program and data.
Some standard communication modes such as EUART are supported in the SH79F085/SH79F165. Also the 20-bit Σ-Δ analog to digital converter (ADC) are incorporated in SH79F085/SH79F165.
For high reliability and low cost, the SH79F085/SH79F165 builds in Watchdog Timer and Low Voltage Reset function. And SH79F085/SH79F165 also supports two power saving modes to reduce power consumption.
1 V2.1
3. Block Diagram
VDD
GND VDDR
A GND
Po wer
Regulato r
Flash ROM 16K Bytes fo r SH79F165 8K Bytes fo r SH79F085
Internal 256 Bytes External 256 Bytes EEPROM 512 Byte
Timer0 (16bit) Timer1 (16bit) Timer2 (16bit) Timer3 (16bit)
External Interrupt
Pipelined 8051 architecture
XTAL1 XTAL2
Internal Oscillato r
Oscillato r
SH79F085/SH79F165
Reset circuit
Watch Do g
Po rt 0 Co nfiguratio n I/O
Po rt 1 Co nfiguratio n I/O
Po rt 2 Co nfiguratio n I/O
EUART
20-bit ADC
PGA
BUZZER
JTAG po rts (fo r debug)
RST
P0.4 - P0.6 P1.0 - P1.7 P2.0 - P2.7
2
4. Pin Configuration SH79F085 Package: TSSOP20
BUZ/P1.0 TDO/RXD/P1.1 TMS/TXD/P1.2
RST/P0.4 XTAL1/T0/P0.5 XTAL2/T1/P0.6
TDI/T2/P1.3 TCK/T2EX/INT0/P1.4
AIN1+/INT1/P1.5 AIN1-/INT2/P1.6
1 2 3 4 5 6 7 8 9 10
SH79F085 Package: SOP24
BUZ/P1.0 TDO/RXD/P1.1 TMS/TXD/P1.2
RST/P0.4 XTAL1/T0/P0.5 XTAL2/T1/P0.6
TDI/T2/P1.3 TCK/T2EX/INT0/P1.4
AIN1+/INT1/P1.5 AIN1-/INT2/P1.6
P1.7 P2.0
1 2 3 4 5 6 7 8 9 10 11 12
SH79F085
SH79F085
SH79F085/SH79F165
20 GND 19 C 18 VDD 17 VDDR 16 AGND 15 P2.7/VREF 14 P2.6/AIN013 P2.5/AIN0+ 12 P2.4/VIN11 P2.3/VIN+
24 GND 23 C 22 VDD 21 VDDR 20 AGND 19 P2.7/VREF 18 P2.6/AIN017 P2.5/AIN0+ 16 P2.4/VIN15 P2.3/VIN+ 14 P2.2/AIN213 P2.1/AIN2+
3
SH79F165 Package: SOP24
BUZ/P1.0 TDO/RXD/P1.1 TMS/TXD/P1.2
RST/P0.4 XTAL1/T0/P0.5 XTAL2/T1/P0.6
TDI/T2/P1.3 TCK/T2EX/INT0/P1.4
AIN1+/INT1/P1.5 AIN1-/INT2/P1.6
P1.7 P2.0
1 2 3 4 5 6 7 8 9 10 11 12
SH79F165
SH79F085/SH79F165
24 GND 23 C 22 VDD 21 VDDR 20 AGND 19 P2.7/VREF 18 P2.6/AIN017 P2.5/AIN0+ 16 P2.4/VIN15 P2.3/VIN+ 14 P2.2/AIN213 P2.1/AIN2+
Note:
The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin Configuration Diagram ). This means when one pin is occupied by a higher priority function (if enabled) cannot be used as the lower priority functional pin, even when the lower priority function is also enabled. Until the higher priority function is closed by software, can the corresponding pin be released for the lower priority function use.
4
Table 4.1 Pin Function
Pin No. SH79F085 SH79F085 (TSSOP20) (SOP24)
11
SH79F165 (SOP24)
1
Pin Name BUZ/P1.0
2 2 2 TDO/RXD/P1.1
3 3 3 TMS/TXD/P1.2
4
4
4
————
RST/P 0.4
5 5 5 XTAL1/T0/P0.5
6 6 6 XTAL2/T1/P0.6
7 7 7 TDI/T2/P1.3
8 8 8 TCK/T2EX/INT0/P1.4
9 9 9 AIN1+/INT1/P1.5
10 10 10 AIN1-/INT2/P1.6
- 11 11 P1.7
- 12 12 P2.0
- 13 13 AIN2+/P2.1
- 14 14 AIN2-/P2.2
11 15 15 VIN+/P2.3
12 16 16 VIN-/P2.4
13 17 17 AIN0+/P2.5
14 18 18 AIN0-/P2.6
15 19 19 VREF/P2.7
16 20 20 AGND
17 21 21 VDDR
18 22 22 VDD 19 23 23.