Document
STB40N60M2, STP40N60M2, STW40N60M2
N-channel 600 V, 0.078 Ω typ., 34 A MDmesh II Plus™ low Qg
2
Power MOSFETs in D PAK, TO-220 and TO-247 packages
Datasheet − production data
TAB
2 3
1
D2PAK
TAB
3 2 1
TO-220
3 2 1
TO-247
Features
Order codes VDS @ TJmax RDS(on) max ID
STB40N60M2 STP40N60M2
650 V
0.088 Ω 34 A
STW40N60M2
• Extremely low gate charge • Lower RDS(on) x area vs previous generation • Low gate input resistance • 100% avalanche tested • Zener-protected
Figure 1. Internal schematic diagram
'7$%
Applications
• Switching applications • LLC converters, resonant converters
Description
* 6
AM01476v1
These devices are N-channel Power MOSFETs developed using a new generation of MDmesh™ technology: MDmesh II Plus™ low Qg. These revolutionary Power MOSFETs associate a vertical structure to the company's strip layout to yield one of the world's lowest on-resistance and gate charge. They are therefore suitable for the most demanding high efficiency converters.
Order codes STB40N60M2 STP40N60M2 STW40N60M2
Table 1. Device summary
Marking
Package
2
D PAK
40N60M2
TO-220
TO-247
Packaging Tape and reel
Tube
May 2014
This is information on a product in full production.
DocID024932 Rev 3
1/21
www.st.com
Contents
Contents
STB40N60M2, STP40N60M2, STW40N60M2
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
4.1 D PAK, STB40N60M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 TO-220, STP40N60M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 TO-247, STW40N60M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21 DocID024932 Rev 3
STB40N60M2, STP40N60M2, STW40N60M2
1 Electrical ratings
Electrical ratings
Symbol
Table 2. Absolute maximum ratings
Parameter
Value
VGS Gate-source voltage ID Drain current (continuous) at TC = 25 °C ID Drain current (continuous) at TC = 100 °C
(1)
IDM Drain current (pulsed) PTOT Total dissipation at TC = 25 °C
(2)
dv/dt Peak diode recovery voltage slope
(3)
dv/dt MOSFET dv/dt ruggedness
Tstg Storage temperature Tj Max. operating junction temperature
1. Pulse width limited by safe operating area. 2. ISD ≤ 34 A, di/dt ≤ 400 A/μs; VDS peak < V(BR)DSS, VDD=400 V. 3. VDS ≤ 480 V
± 25 34 22 136 250 15 50
- 55 to 150
Unit V A A A W
V/ns V/ns °C °C
Table 3. Thermal data
Symbol
Parameter
Rthj-case Thermal resistance junction-case max
(1)
Rthj-pcb Thermal resistance junction-pcb max Rthj-amb Thermal resistance junction-ambient max
1. When mounted on 1 inch² FR-4, 2 Oz copper board
D2PAK 30
Value TO-220
0.50
62.5
Unit TO-247
°C/W
°C/W
50 °C/W
Symbol
Table 4. Avalanche characteristics
Parameter
Value
Avalanche current, repetitive or not IAR repetitive (pulse width limited by Tjmax)
Single pulse avalanche energy (starting EAS Tj=25°C, ID= IAR; VDD=50 V)
6 500
Unit A mJ
DocID024932 Rev 3
3/21
21
Electrical characteristics
STB40N60M2, STP40N60M2, STW40N60M2
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Symbol
Parameter
Table 5. On /off states Test conditions
Drain-source V(BR)DSS breakdown voltage
VGS = 0, ID = 1 mA
Zero gate voltage
IDSS drain current
IGSS
Gate-body leakage current
VGS = 0, VDS = 600 V VGS = 0, VDS = 600 V, TC=125 °C
VDS = 0, VGS = ± 25 V
VGS(th) RDS(on)
Gate threshold voltage VDS = VGS, ID = 250 μA
Static drain-source on-resistance
VGS = 10 V, ID = 17 A
Min. Typ. Max. Unit 600 V
1 μA 100 μA
±10 μA 2 3 4V
0.078 0.088 Ω
Symbol
Parameter
Table 6. Dynamic Test conditions
Min. Typ. Max. Unit
Ciss Coss
Crss
Input capacitance Output capacitance Reverse transfer capacitance
VDS = 100 V, f = 1 MHz, VGS = 0
- 2500 - pF - 117 - pF - 2.4 - pF
(1) Equivalent output Coss eq. capacitance
VDS = 0 to 480 V, VGS = 0
- 342 - pF
Intrinsic gate RG resistance
f = 1 MHz, ID = 0
- 4.4 - Ω
Qg Total gate charge
VDD = 480 V, ID = 34 A,
Qgs Gate-source charge VGS = 10 V
Qgd Gate-drain charge
(see Figure 17)
- 57 - nC - 10 - nC - 25.5 - nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
Symbol
Table 7. Switching times
Parameter
Test conditions
td(on) tr
td(off) tf
Turn-on delay time Rise time Turn-off-delay time Fall t.