TS25L16APP

TS25L16APP 16 Mbit Serial Flash memory with 75 MHz Dual and Quad SPI bus Interface Features Architectural Advantages n Single power supply operation Full voltage range: 2.7 to 3.6 V read and program operations n Memory Architecture 32ea sectors with 512 Kb each n Program Page Program (up to 256 bytes) in 0.3 ms (typical) Page Write (up to 256 bytes) in 2.8 ms (typical) Program cycles are on a page by page basis n Erase 2ms typical Page Erase Time 2ms typical SubSector Erase Time 32ms typical Sector Erase time 1 sec typical Bulk Erase time n Cycling Endurance 100,000 P/E cycles per sector typical n Data Retention 20 years typical n Device ID JEDEC standard two-byte electronic signature n Package Option Industry Standard Pin-outs 8-pin SOP 208 mil 8-pin SOP 150 mil 8-pin PDIP 300 mil Performance Characteristics n Speed 75 MHz clock rate (maximum) n Dual/Quad Output Speed 150 MHz/300 MHz an equivalent clock rate (maximum) n Power Saving Standby Mode Standby Mode 1 µA (typical) Deep Power-down Mode 1 µA (typical) Memory Protection Features n Memory Protection W# (SO2) pin works in conjunction with Status Register Bits to protect specified memory areas Status Register Block Protection bits (BP3, BP2, BP1, BP0) in status register configure parts of memory as read-only Software Features n SPI Bus Compatible Serial Interface May 2009 1/1 Terra Semiconductor Contents TS25L16APP 1 Description . . . . . . . . . . . . . . . . . . . . . ....