Document
RL78/G1F
RENESAS MCU
Datasheet
R01DS0246EJ0100 Rev. 1.00
Apr 06, 2015
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
• VDD = single power supply voltage of 1.6 to 5.5 V which can operate a 1.8 V device at a low voltage
• HALT mode • STOP mode • SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline • Minimum instruction execution time: Can be changed
from high speed (0.03125 s: @ 32 MHz operation with high-speed on-chip oscillator) to ultra-low speed (30.5 s: @ 32.768 kHz operation with subsystem clock) • Multiply/divide/multiply & accumulate instructions are supported. • Address space: 1 MB • General-purpose registers: (8-bit register 8) 4 banks • On-chip RAM: 5.5 KB
Code flash memory
• Code flash memory: 32/64 KB • Block size: 1 KB • Prohibition of block erase and rewriting (security
function) • On-chip debug function • Self-programming (with boot swap function/flash shield
window function)
Data flash memory
• Data flash memory: 4 KB • Back ground operation (BGO): Instructions can be
executed from the program memory while rewriting the data flash memory. • Number of rewrites: 1,000,000 times (TYP.) • Voltage of rewrites: VDD = 1.8 to 5.5 V
High-speed on-chip oscillator
• Select from 64 MHz, 48 MHz, 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 5.5 V, TA = -20 to +85°C)
Operating ambient temperature
• TA = 40 to +85°C (A: Consumer applications) • TA = 40 to +105°C (G: Industrial applications)
Power management and reset function
• On-chip power-on-reset (POR) circuit • On-chip voltage detector (LVD) (Select interrupt and
reset from 14 levels)
Data transfer controller (DTC)
• Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode
• Activation sources: Activated by interrupt sources. • Chain transfer function
R01DS0246EJ0100 Rev. 1.00 Apr 06, 2015
Event link controller (ELC)
• Event signals of 22 types can be linked to the specified peripheral function.
Serial interfaces
• CSI: 3 to 6 channels • UART/UART (LIN-bus supported): 3 channels • I2C/simplified I2C: 3 to 6 channels • IrDA: 1 channel
Timer
• 16-bit timer: 9 channels (Timer Array Unit (TAU): 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels (with PWMOPA), Timer RG: 1 channel, Timer RX: 1 channel)
• 12-bit interval timer: 1 channel • Real-time clock: 1 channel (calendar for 99 years, alarm
function, and clock correction function) • Watchdog timer: 1 channel (operable with the dedicated
low-speed on-chip oscillator)
A/D converter
• 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V) • Analog input: 8 to 17 channels • Internal reference voltage (1.45 V) and temperature
sensor
D/A converter
• 8-bit resolution D/A converter (VDD = 1.6 to 5.5 V) • Analog output: 1 or 2 channels • Output voltage: 0 V to VDD • Real-time output function
Comparator
• 2 channels (pin selector is provided for 1 channel)
• Incorporates a function for the output of a timer window
in combination with the timer array unit. • The external reference voltage or internal reference
voltage can be selected as the reference voltage.
Programmable gain amplifier (PGA)
• 1 channel
I/O port
• I/O port: 20 to 58 (N-ch open drain I/O [withstand voltage of 6 V]: 2 to 4, N-ch open drain I/O [VDD withstand voltage/EVDD withstand voltage]: 10 to 16)
• Can be set to N-ch open drain, TTL input buffer, and onchip pull-up resistor
• Different potential interface: Can connect to a 1.8/2.5/3 V device
• On-chip key interrupt function • On-chip clock output/buzzer output controller
Others
• On-chip BCD (binary-coded decimal) correction circuit
Remark The functions mounted depend on the
product. See 1.6 Outline of Functions.
Page 1 of 140
RL78/G1F
1. OUTLINE
ROM, RAM capacities
Flash ROM Data flash
RAM
64 KB 32 KB
4 KB 4 KB
5.5 KB Note 5.5 KB Note
24 pins R5F11B7E R5F11B7C
32 pins R5F11BBE R5F11BBC
RL78/G1F 36 pins
R5F11BCE R5F11BCC
48 pins R5F11BGE R5F11BGC
64 pins R5F11BLE R5F11BLC
Note
This is about 4.5 KB when performing self-programming and rewriting the data flash memory (For details, see CHAPTER 3 CPU ARCHITECTURE in the RL78/G1F User’s Manual).
R01DS0246EJ0100 Rev. 1.00 Apr 06, 2015
Page 2 of 140
RL78/G1F
1.2 Ordering Information
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G1F
Part No. R 5 F 1 1 B L E A x x x F B # 3 0
1. OUTLINE
Packaging specification #U0: Tray (HWQFN, WFLGA, FLGA) #30: Tray (LFQFP, LQFP) #W0: Embossed Tape (HWQFN, WFLGA, FLGA) #50: Embossed Tape (LFQFP, LQFP)
Package type: FP: LQFP, 0.80 mm pitch FB: LFQFP, 0.50 mm pitch NA:HWQFN, 0.50 mm pitch LA: WFLGA, 0.50 mm pitch
ROM number (Omitted with blank products)
Fields of application: A: Consumer applications, TA = -40 to +85C G: Industrial applications, TA = -40 to +105C
ROM capacity: C: 32 KB E: 64 KB
Pin count: 7: 24-pin B: 32-pin C: 36-pin G: 48-pin L: 64-pin
RL78/G1F
Memory type: F : Flash memory
Renesas MCU
Renesas semiconductor product
R01DS0246EJ01.