Document
OptiMOS®-T2 Power-Transistor
Features • N-channel - Enhancement mode • AEC qualified • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green Product (RoHS compliant) • 100% Avalanche tested
IPB80N04S4L-04 IPI80N04S4L-04, IPP80N04S4L-04
Product Summary V DS R DS(on),max (SMD version) ID
40 V 4.0 mΩ 80 A
PG-TO263-3-2 PG-TO262-3-1 PG-TO220-3-1
Type IPB80N04S4L-04 IPI80N04S4L-04 IPP80N04S4L-04
Package PG-TO263-3-2 PG-TO262-3-1 PG-TO220-3-1
Marking 4N04L04 4N04L04 4N04L04
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol
Conditions
Continuous drain current1)
I D T C=25°C, V GS=10V
T C=100°C, V GS=10V2)
Pulsed drain current2)
I D,pulse T C=25°C
Avalanche energy, single pulse2) E AS I D=40A
Avalanche current, single pulse I AS -
Gate source voltage
V GS
-
Power dissipation
P tot T C=25°C
Operating and storage temperature T j, T stg -
IEC climatic category; DIN IEC 68-1 -
-
Value 80
80
320 100 80 +20/-16 71 -55 ... +175 55/175/56
Unit A
mJ A V W °C
Rev. 1.0
page 1
2010-04-13
Parameter
Symbol
IPB80N04S4L-04 IPI80N04S4L-04, IPP80N04S4L-04
Conditions
min.
Values typ.
Unit max.
Thermal resistance, junction - case R thJC
Thermal resistance, junction ambient, leaded
R thJA
SMD version, device on PCB
R thJA
-
-
minimal footprint 6 cm2 cooling area3)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current
Gate-source leakage current Drain-source on-state resistance
V (BR)DSS V GS=0V, I D= 1mA
V GS(th) V DS=V GS, I D=35µA
I DSS
V DS=40V, V GS=0V
V DS=18V, V GS=0V, T j=85°C2)
I GSS
V GS=20V, V DS=0V
R DS(on) V GS=4.5V, I D=40A
V GS=4.5V, I D=40A, SMD version
V GS=10 V, I D=80 A
V GS=10 V, I D=80 A, SMD version
- - 2.1 K/W - - 62 - - 62 - - 40
40 -
-V
1.2 1.7 2.2
- 0.02 1 µA
- 1 20
- - 100 nA - 5.1 6 mΩ
- 4.8 5.7
- 3.7 4.3
- 3.4 4.0
Rev. 1.0
page 2
2010-04-13
Parameter
Dynamic characteristics2) Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time
Gate Charge Characteristics2) Gate to source charge Gate to drain charge Gate charge total Gate plateau voltage
Reverse Diode Diode continous forward current2) Diode pulse current2)
Diode forward voltage
Reverse recovery time2)
Symbol
IPB80N04S4L-04 IPI80N04S4L-04, IPP80N04S4L-04
Conditions
min.
Values typ.
Unit max.
C iss C oss Crss
V GS=0V, V DS=25V, f =1MHz
- 3610 4690 pF - 650 840 - 30 69
t d(on)
- 7 - ns
tr
V DD=20V, V GS=10V,
-
12
-
t d(off)
I D=80A, R G=3.5Ω
- 22 -
t f - 31 -
Q gs Q gd Qg V plateau
V DD=32V, I D=80A, V GS=0 to 10V
- 12 16 nC - 5 12 - 46 60 - 3.2 - V
IS I S,pulse
V SD
T C=25°C
V GS=0V, I F=80A, T j=25°C
t rr
V R=20V, I F=50A, di F/dt =100A/µs
- - 80 A - - 320 - 0.9 1.3 V
- 39 - ns
Reverse recovery charge2)
Q rr
- 35 - nC
1) Current is limited by bondwire; with an R thJC = 2.1K/W the chip is able to carry 98A at 25°C.
2) Defined by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air.
Rev. 1.0
page 3
2010-04-13
1 Power dissipation P tot = f(T C); V GS ≥ 6 V
IPB80N04S4L-04 IPI80N04S4L-04, IPP80N04S4L-04
2 Drain current I D = f(T C); V GS ≥ 6 V; SMD
75
80 62.5
50 60
P tot [W] I D [A]
37.5 25
12.5
40 20
0 0 50 100 150 T C [°C]
3 Safe operating area I D = f(V DS); T C = 25 °C; D = 0; SMD parameter: t p
1000
0 200 0
50 100 150 T C [°C]
4 Max. transient thermal impedance Z thJC = f(t p) parameter: D =t p/T
101
200
I D [A] Z thJC [K/W]
100 10
1 µs
10 µs 100 µs 1 ms
100 0.5
10-1
0.1 0.05 0.01
10-2
single pulse
1 0.1
Rev. 1.0
1 10 V DS [V]
100
10-3 10-6
10-5
10-4
10-3
10-2
10-1
100
t p [s]
page 4
2010-04-13
5 Typ. output characteristics I D = f(V DS); T j = 25 °C; SMD parameter: V GS
IPB80N04S4L-04 IPI80N04S4L-04, IPP80N04S4L-04
6 Typ. drain-source on-state resistance R DS(on) = f(I D); T j = 25 °C; SMD parameter: V GS
300
10 V
5V
240
180
120
4.5 V 4V
15
13
11
3.5 V
9
7
4V
I D [A] R DS(on) [mΩ]
60
0 0
3.5 V
3V 2.5 V
123 V DS [V]
4
4.5 V
5
5V
10 V
3 0 30 60 90 120 150 I D [A]
7 Typ. transfer characteristics I D = f(V GS); V DS = 6V parameter: T j
8 Typ. drain-source on-state resistance R DS(on) = f(T j); I D = 80 A; V GS = 10 V; SMD
240 6.5
-55 °C
6
180
25 °C 175 °C
5.5 5
I D [A] R DS(on) [mΩ]
4.5 120
4
3.5
60 3
2.5
02
12345
-60 -20 20
60 100 140 180
V GS [V]
T j [°C]
Rev. 1.0
page 5
2010-04-13
V GS(th) [V] C [pF]
9 Typ. gate threshold voltage V GS(th) = f(T j); V GS = V DS parameter: I D
2
1.75 1.5
1.25
350 µA 35 µA
1
IPB80N04S4L-04 IPI80N04S4L-04, IPP80N04S4L-04
10 Typ. capacitances C = f(V DS); V GS = 0 V; f = 1 MHz
104
Ciss
103
Coss
102
Crss
0.75 -60 -20 20 60 100 140 180 T j [°C]
101 0
5 10 15 20 25 30 V DS [V]
11 Typical.