Document
Freescale Semiconductor Data Sheet: Technical Data
Document Number: MMA68xx Rev. 5, 03/2012
Dual-Axis SPI Inertial Sensor
MMA68xx, a SafeAssure solution, is a SPI-based, 2-axis, medium-g, overdamped lateral accelerometer designed for use in automotive airbag systems.
Features • ±20g to ±120g full-scale range, independently specified for each axis • 3.3V or 5V single supply operation • SPI-compatible serial interface • 10-bit digital signed or unsigned SPI data output • Independent programmable arming functions for each axis • Twelve low-pass filter options, ranging from 50 Hz to 1000 Hz • Optional offset cancellation with > 6s averaging period and < 0.25 LSB/s slew
rate • Pb-Free 16-Pin QFN-6 by 6 Package
Referenced Documents • AECQ100, Revision G, dated May 14, 2007 (http://www.aecouncil.com/)
MMA68xx
Bottom View
16 LEAD QFN 6 mm by 6 mm CASE 2086-01
Top View
VSSA N/C N/C VSSA
ORDERING INFORMATION
Device
X-Axis Range
Y-Axis Range
MMA6811BKW MMA6813BKW MMA6821BKW MMA6823BKW MMA6825BKW MMA6826BKW MMA6827BKW MMA6811BKWR2 MMA6813BKWR2 MMA6821BKWR2 MMA6823BKWR2 MMA6825BKWR2 MMA6826BKWR2 MMA6827BKWR2
±60g ±50g ±120g ±120g ±100g ±60g ±120g ±60g ±50g ±120g ±120g ±100g ±60g ±120g
±25g ±50g ±25g ±60g ±100g ±60g ±120g ±25g ±50g ±25g ±60g ±100g ±60g ±120g
Shipping
Tubes Tubes Tubes Tubes Tubes Tubes Tubes Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel
16 15 14 13
VREGA 1 VSS 2
VREG 3 VSS 4
17 56
12 CS 11 MOSI 10 SCLK 9 VCC 78
ARM_Y/PCM_Y ARM_X/PCM_X
TEST/VPP MISO
Pin Connections
© 2010-2012 Freescale Semiconductor, Inc. All rights reserved.
Application Diagram
VCC
VCC
CS
VREG
SCLK
VREGA
MOSI
MISO
C1 C2 C3
MMA68xx
VSSA VSS VPP/TEST
ARM_X ARM_Y
CS_A
CS_D
SCLK1
SCLK2
MOSI1
MOSI2
MISO1
MISO2
Main MCU
CS SCLK MOSI MISO
Deployment IC
DEPLOY_EN1 DEPLOY_EN2
Figure 1. Application Diagram
Table 1. External Component Recommendations
Ref Des
Type
Description
C1
Ceramic
0.1 μF, 10%, 10V Minimum, X7R
C2
Ceramic
1 μF, 10%, 10V Minimum, X7R
C3
Ceramic
1 μF, 10%, 10V Minimum, X7R
Purpose VCC Power Supply Decoupling Voltage Regulator Output Capacitor (CREG) Voltage Regulator Output Capacitor (CREGA)
Device Orientation
xxxxxxx xxxxxxx
xxxxxxx xxxxxxx
xxxxxxx xxxxxxx
X: 0g Y: -1g
X: +1g Y: 0g
X: 0g Y: +1g
xxxxxxx xxxxxxx
X: -1g Y: 0g
X: 0g Y: 0g
EARTH GROUND
Figure 2. Device Orientation Diagram
X: 0g Y: 0g
MMA68xx 2
Sensors Freescale Semiconductor, Inc.
Internal Block Diagram
Over-Damped Y-Axis g-Cell
Self Test
Over-Damped X-Axis g-Cell
SINC Filter
ΣΔ Converter
Clock & bias Generator
IIR Low-Pass Filter
Compensation
Linear Interpolation
Offset Cancellation
Clock CRC Generation
Offset Monitor
Y-Axis Register Array
Output Scaling
SPI Mismatch Verification
VREG VREGA VCC
1 MHz
Analog Regulator
1 MHz
VREGA
Clock & bias Generator
ΣΔ Converter
8 MHz Oscillator
Digital
Voltage OTP Memory
Regulator Monitoring Array
VREG
X-Axis Register Array
SINC Filter
Clock CRC Generation
Clock Monitoring
IIR Low-Pass Filter
Compensation
Linear Interpolation
Offset Monitor
Offset Cancellation
Output Scaling
ARM_Y Y-Axis SPI
SPI I/O
X-Axis SPI
ARM_X
VPP VCC VREG VSS VREGA VSSA ARM_Y
CS SCLK MOSI MISO
ARM_X
Figure 3. Block Diagram
Sensors Freescale Semiconductor, Inc.
MMA68xx 3
1 Pin Connections
VSSA N/C N/C VSSA
16 15 14 13
VREGA VSS
VREG VSS
1 2 3 4
17 567
12 CS 11 MOSI 10 SCLK 9 VCC 8
ARM_Y/PCM_Y ARM_X/PCM_X
TEST/VPP MISO
Figure 4. 16-Pin QFN Package, Top View
Table 2. Pin Description
Pin
Pin Name
Formal Name
Definition
1 VREGA
Analog Supply
This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between this pin and VSSA. Reference Figure 1.
2 VSS Digital GND This pin is the power supply return node for the digital circuitry.
3 VREG
Digital Supply
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1.
4 VSS Digital GND This pin is the power supply return node for the digital circuitry.
5 ARM_Y/
Y-Axis The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.5. When the
PCM_Y Arm Output / arming output is selected, ARM_Y can be configured as an open drain, active low output with a pullup current;
PCM Output or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a digital
output with PCM signal proportional to the Y axis acceleration data. Reference Section 3.8.9 and Section
3.8.9.1. If unused, this pin must be left unconnected.
6 ARM_X/
X-Axis The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.5. When the
PCM_X Arm Output / arming output is selected, ARM_X can be configured as an open drain, active low output with a pullup current;
PCM Output or an open drain, active high output with a pulld.