Document
4Gb DDR3 SDRAM
4Gb DDR3 SDRAM
Lead-Free&Halogen-Free (RoHS Compliant)
H5TQ4G83AFR-xxC H5TQ4G83AFR-xxI H5TQ4G83AFR-xxL H5TQ4G83AFR-xxJ H5TQ4G63AFR-xxC H5TQ4G63AFR-xxI H5TQ4G63AFR-xxL H5TQ4G63AFR-xxJ
* SK Hynix reserves the right to change products or specifications without notice.
Rev. 1.1/ Jan 2013
1
Revision History
Revision No. 1.0 1.1
History Official Version Release
x8 IDD update
Draft Date Oct. 2012 Jan. 2013
Remark
Rev. 1.1/ Jan 2013
2
Description
The H5TQ4G83AFR-xxC,H5TQ4G63AFR-xxC, H5TQ4G83AFR-xxI, H5TQ4G63AFR-xxI, H5TQ4G83AFR-xxL, H5TQ4G63AFR-xxL,H5TQ4G83AFR-xxJ and H5TQ4G63AFR-xxJ are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported
• Programmable additive latency 0, CL-1, and CL-2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8 9 and 10
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on the fly
• 8banks
• Average Refresh Cycle (Tcase of0 oC~95oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC Commercial Temperature( 0oC ~ 85 oC) Industrial Temperature( -40oC ~ 95 oC)
• JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
* This product in compliance with the RoHS directive.
Rev. 1.1/ Jan 2013
3
ORDERING INFORMATION
Part No.
H5TQ4G83AFR-*xxC H5TQ4G83AFR-*xxI H5TQ4G83AFR-*xxL H5TQ4G83AFR-*xxJ H5TQ4G63AFR-*xxC H5TQ4G63AFR-*xxI H5TQ4G63AFR-*xxL H5TQ4G63AFR-*xxJ
Configuration 512M x 8
256M x 16
Power Consumption
Normal Consumption
Low Power Consumption (IDD6 Only)
Normal Consumption
Low Power Consumption (IDD6 Only)
Temperature
Commercial Industrial
Commercial Industrial Commercial Industrial Commercial Industrial
* xx means Speed Bin Grade
Package 78ball FBGA
96ball FBGA
OPERATING FREQUENCY
Speed
.