Document
® ISO2-CMOS MT8960/61/62/63/64/65/66/67
Integrated PCM Filter Codec
Features
• ST-BUS™ compatible • Transmit/Receive filters & PCM Codec in one
I.C • Meets AT&T D3/D4 and CCITT G711 and G712 • µ-Law: MT8960/62/64/67 • A-Law: MT8961/63/65/67 • Low power consumption:
Op.: 30 mW typ. Stby.: 2.5 mW typ. • Digital Coding Options: MT8964/65/66/67 CCITT Code MT8960/61/62/63 Alternative Code • Digitally controlled gain adjust of both filters • Analog and digital loopback • Filters and codec independently user accessible for testing • Powerdown mode available • 2.048 MHz master clock input • Up to six uncommitted control outputs • ±5V ±5% power supply
ISSUE 10
May 1995
Ordering Information
MT8964/65AC
18 Pin Ceramic DIP
MT8960/61/64/65AE MT8962/63AE MT8962/63/66/67AS
18 Pin Plastic DIP 20 Pin Plastic DIP 20 Pin SOIC
0°C to+70°C
Description
Manufactured in ISO2-CMOS, these integrated filter/ codecs are designed to meet the demanding performance needs of the digital telecommunications industry, e.g., PABX, Central Office, Digital telephones.
ANUL
VX
SD0 SD1 SD2 SD3 SD4 SD5
VR
Transmit Filter
Analog to Digital PCM
Encoder
Output Register
Output Register
A Register 8-Bits
B-Register 8-Bits
Control Logic
Receive Filter
PCM Digital to Analog Decoder
Input Register
VRef GNDA GNDD VDD VEE
Figure 1 - Functional Block Diagram
DSTo CSTi CA F1i C2i
DSTi
6-19
MT8960/61/62/63/64/65/66/67 ISO2-CMOS
MT8960/61/64/65
CSTi DSTi
C2i DSTo VDD
F1i CA SD3 SD2
1 2
3 4 5
6 7 8 9
18 GNDD 17 VRef 16 GNDA 15 VR 14 ANUL 13 VX 12 VEE 11 SD0 10 SD1
18 PIN CERDIP/PDIP
MT8962/63/66/67
CSTi DSTi
C2i DSTo VDD
SD5 SD4
F1i CA SD3
1 2
3 4 5
6 7 8 9 10
20 GNDD 19 VRef 18 GNDA 17 VR 16 ANUL 15 VX
14 VEE 13 SD0 12 SD1
11 SD2
20 PIN PDIP/SOIC
Pin Description
Figure 2 - Pin Connections
Pin Name
Description
CSTi
Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec.
Three modes of operation may be effected by applying to this input a logic high (VDD), logic low (GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i.
Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs.
DSTi Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible.
C2i Clock Input is a TTL-compatible 2.048 MHz clock.
DSTo Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM word.
VDD Positive power Supply (+5V).
F1i Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input, PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i, and provides frame and channel synchronization.
CA Control Address is a three-level digital input which enables PCM input and output and determines into which control register (A or B) the serial data, presented to CSTi, is stored.
SD3 System Drive Output is an open drain output of an N-channel transistor w.