MK2302-01

MULTIPLIER AND ZERO DELAY BUFFER DATASHEET MK2302-01 Description The MK2302-01 is a high performance Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase Locked Loop (PLL) techniques. The chip is part of IDT’s ClockBlocksTM family and was designed as a performance upgrade to meet today’s higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The MK2302-01 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices. Features 8-pin SOIC package Pb (lead) free package Low input to output skew of 250 ps max Absolute jitter ± 500 ps Propagation Delay ± 350 ps Ability to choose between different multipliers from 0.5X to 16X Output clock frequency up to 168 MHz at 3.3 V Can recover degraded input clock duty cycle Output clock duty cycle of 45/55 Full CMOS clock swings with 25mA drive capability at TTL levels Advanced, low power CMOS process Operating voltage of 3.3 V or 5 V Industrial temperature version available Block Diagram IC L K S 1 :0 F B IN divide by N Phase D e te cto r, C ha rg e Pump, and Loop F ilt...