Document
MGA-634P8 Ultra Low Noise, High Linearity Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-634P8 is an economical, easyto-use GaAs MMIC Low Noise Amplifier (LNA). The LNA has low noise and high linearity achieved through the use of Avago Technologies’ proprietary 0.25um GaAs Enhancement-mode pHEMT process. It is housed in a miniature 2.0 x 2.0 x 0.75mm3 8-pin Quad-Flat-Non-Lead (QFN) package. It is designed for optimum use from 1.5 GHz up to 2.3 GHz. The compact footprint and low profile coupled with low noise, high gain and high linearity make the MGA-634P8 an ideal choice as a low noise amplifier for cellular infrastructure for GSM and CDMA. For optimum performance at lower frequency from 450MHz up to 1.5GHz, MGA-633P8 is recommended. For optimum performance at higher frequency from 2.3GHz up to 4GHz, MGA-635P8 is recommended. All these 3 products, MGA633P8, MGA-634P8 and MGA-635P8 share the same package and pinout configuration.
Pin Configuration and Package Marking
2.0 x 2.0 x 0.75 mm3 8-lead QFN
[1] [8] [2] [7]
[3] 34X [6]
[4] [5]
[8] [7]
[6] [5]
[1] [2]
[3] [4]
Top View
Pin 1 – Vbias Pin 2 – RFinput Pin 3 – Not Used Pin 4 – Not Used
Bottom View
Pin 5 – Not Used Pin 6 – Not Used Pin 7 – RFoutput/Vdd Pin 8 – Not Used Centre tab - Ground
Features
Ultra Low noise Figure High linearity performance GaAs E-pHEMT Technology [1] Low cost small package size: 2.0x2.0x0.75 mm3 Excellent uniformity in product specifications Tape-and-Reel packaging option available
Specifications
1.9 GHz; 5V, 48mA
17.4 dB Gain 0.44 dB Noise Figure 15.5 dB Input Return Loss 36 dBm Output IP3 21 dBm Output Power at 1dB gain compression
Applications
Low noise amplifier for cellular infrastructure for GSM TDS-CDMA, and CDMA.
Other ultra low noise application.
Simplified Schematic
Vdd
Rbias
C5 R1
R2 C6
C3 L1
C4 L2
Note: Package marking provides orientation and identification “34” = Device Code, where X is the month code.
Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 70 V (Class A) ESD Human Body Model = 500 V (Class 1B) Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control.
RFin C1
[1] bias [8]
[2] [7]
[3] [6] [4] [5]
C2
RFout
Notes: The schematic is shown with the assumption that similar PCB is used
for all MGA-633P8, MGA-634P8 and MGA-635P8. Detail of the components needed for this product is shown in Table 1. Enhancement mode technology employs positive gate voltage,
thereby eliminating the need of negative gate voltage associated
with conventional depletion mode devices. Good RF practice requires all unused pins to be earthed.
Absolute Maximum Rating [1] TA=25°C
Symbol Vdd
Vbias Pin,max
Pdiss Tj Tstg
Parameter Device Voltage, RF output to ground Gate Voltage
CW RF Input Power (Vdd = 5.0V, Id = 50 mA) Total Power Dissipation [2]
Junction Temperature
Storage Temperature
Units V
V dBm
W °C °C
Absolute Maximum 5.5
0.7 +20
0.5 150 -65 to 150
Thermal Resistance
Thermal Resistance [3] (Vdd = 5.0V, Idd = 50mA) jc = 62°C/W
Notes: 1. Operation of this device in excess of any of
these limits may cause permanent damage. 2. Power dissipation with device turned on.
Board temperature TB is 25°C. Derate at 16mW/°C for TB>119°C. 3. Thermal resistance measured using Infra-Red Measurement Technique
Electrical Specifications [1], [4]
RF performance at TA = 25°C, Vdd = 5V, Rbias = 5.6 kOhm, 1.9 GHz, measured on demo board in Figure 1 with component listed in Table 1 for 1.9 GHz matching.
Symbol
Parameter and Test Condition
Units Min. Typ. Max.
Idd Drain Current Gain Gain
mA 37 48 61 dB 16.1 17.4 19.1
OIP3 [2]
Output Third Order Intercept Point
dBm 33
36
NF [3]
Noise Figure
dB 0.44 0.69
OP1dB
Output Power at 1dB Gain Compression
dBm 21
IRL Input Return Loss, 50 source
dB 15.5
ORL Output Return Loss, 50 load
dB 13
REV ISOL
Reverse Isolation
dB 30
Notes: 1. Measurements at 1.9 GHz obtained using demo board described in Figure 1. 2. OIP3 test condition: FRF1 = 1.9 GHz, FRF2 = 1.901 GHz with input power of -10dBm per tone. 3. For NF data, board losses of the input have not been de-embedded. 4. Use proper bias, heatsink and derating to ensure maximum device temperature is not exceeded. See absolute maximum ratings and application
note for more details.
2
Product Consistency Distribution Charts [1, 2]
LSL USL
Idd Max: 61 Min: 37 Mean: 48
Noise Figure Max: 0.69 Mean: 0.44
USL
36 38 40 42 44 46 48 50 52 54 56 58 60 62 Figure 1. Idd @ 1.9GHz, 5V, 48mA Mean = 48
0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Figure 2. Noise Figure @1.9GHz, 5V, 48mA Mean = 0.44
LSL
OIP3 Min: 33 Mean: 36
LSL USL
Gain Max: 19.1 Min: 16.1 Mean: 17.4
33 34 35 36 Figure 3. OIP3 @ 1.9GHz, 5V, 48mA Mean = 36
37
16 16.5 17 17.5 18 18.5 19 Figure 4. Gain @1.9GHz, 5V, 48mA Mean = 17.4
Notes: 1. Distribution data samples are 500 samples taken from 3 different wafers. Future wafers alloc.