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HCF4035B Dataheets PDF



Part Number HCF4035B
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description 4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER
Datasheet HCF4035B DatasheetHCF4035B Datasheet (PDF)

HCC/HCF4035B 4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER . . . . . . . . . . . . . 4-STAGE CLOCKED SHIFT OPERATION SYNCHRONOUS PARALLEL ENTRY ON ALL 4 STAGES JK INPUTS ON FIRST STAGE ASYNCHRONOUS TRUE/COMPLEMENT CONTROL ON ALL OUTPUTS STATIC FLIP-FLOP OPERATION ; MASTERSLAVE CONFIGURATION BUFFERED INPUTS AND OUTPUTS HIGH SPEED 12MHz (typ.) AT VDD = 10V QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT.

  HCF4035B   HCF4035B



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HCC/HCF4035B 4-STAGE PARALLEL IN/PARALLEL OUT SHIFT REGISTER . . . . . . . . . . . . . 4-STAGE CLOCKED SHIFT OPERATION SYNCHRONOUS PARALLEL ENTRY ON ALL 4 STAGES JK INPUTS ON FIRST STAGE ASYNCHRONOUS TRUE/COMPLEMENT CONTROL ON ALL OUTPUTS STATIC FLIP-FLOP OPERATION ; MASTERSLAVE CONFIGURATION BUFFERED INPUTS AND OUTPUTS HIGH SPEED 12MHz (typ.) AT VDD = 10V QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURR 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N°. 13A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF ”B” SERIES CMOS DEVICES” Whith JK inputs connected together, the first stage becomes a D flip-flop. An asynchronous common RESET is also provided. EY (Plastic Package) F (Ceramic Frit Seal Package) M1 (Micro Package) C1 (Plastic Chip Carrier) ORDER CODES : HCC4035BF HCF4035BM1 HCF4035BEY HCF4035BC1 DESCRIPTION The HCC4035B (extended temperature range) and HCF4035B (intermediate temperature range) are monolithic integrated circuit, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4035B is a fourstage clocked signal serial register with provision for synchronous PARALLEL inputs to each stage and SERIAL inputs to the first stage via JK logic. Register stages 2, 3, and 4 are coupled in a serial D flipflop configuration when the register is in the serial mode (PARALLEL/SERIAL control low). Parallel entry into each register stage is permitted when the PARALLEL/SERIAL control is high. In the parallel or serial mode information is transferred on positive clock transitions. When the TRUE/COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. The TRUE/COMPLEMENT control functions asynchronously with respect to the CLOCK signal. JK input logic is provided on the first stage SERIAL input to minimize logic requirements particularly in counting and sequence-generation applications. July 1989 PIN CONNECTIONS 1/14 HCC/HCF4035B FUNCTIONAL DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DD* Vi II Pt ot Parameter Supply Voltage : HC C Types H C F Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for T o p = Full Package-temperature Range Operating Temperature : HCC Types H CF Types Storage Temperature Value – 0.5 to + 20 – 0.5 to + 18 – 0.5 to V DD + 0.5 ± 10 200 100 – 55 to + 125 – 40 to + 85 – 65 to + 150 Unit V V V mA mW mW °C °C °C Top Tstg Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not .


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