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MPC9230 Dataheets PDF



Part Number MPC9230
Manufacturers Motorola
Logo Motorola
Description 800 MHz Low Voltage PECL Clock Synthesizer
Datasheet MPC9230 DatasheetMPC9230 Datasheet (PDF)

MOTOROLA Freescale Semiconductor, Inc. Order number: MPC9230 Rev 4, 07/2004 SEMICONDUCTOR TECHNICAL DATA 800 MHz Low Voltage PECL Clock Synthesizer The MPC9230 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 50 MHz to 800 MHz1 and the support of differential PECL output signals the device meets the needs of the most demanding clock appl.

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MOTOROLA Freescale Semiconductor, Inc. Order number: MPC9230 Rev 4, 07/2004 SEMICONDUCTOR TECHNICAL DATA 800 MHz Low Voltage PECL Clock Synthesizer The MPC9230 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 50 MHz to 800 MHz1 and the support of differential PECL output signals the device meets the needs of the most demanding clock applications. Features • • • • • • • • • • • • • • • 50 MHz to 800 MHz1 synthesized clock output signal Differential PECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock input 3.3V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 32 lead LQFP and 28 PLCC packaging 32-Lead Pb-free Package Available SiGe Technology Ambient temperature range -40°C to +85°C Pin and function compatible to the MC12430 MPC9230 800 MHz LOW VOLTAGE CLOCK SYNTHESIZER Freescale Semiconductor, Inc... FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 FA SUFFIX 32-LEAD TQFP PACKAGE CASE 873A-03 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz.1 Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 8⋅M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz1). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50Ω to VCC – 2.0V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. 1. The VCO frequency range of 800–1600 MHz is available at an ambient temperature range of 0 to 70°C. At –40 to +85°C, the VCO frequency (output frequency) is limited to max. 1500 MHz (750 MHz) © Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC9230 XTAL_IN XTAL_OUT FREF_EXT XTAL 10 – 20 MHz ÷16 Ref VCO ÷2 PLL 800 – 1800 MHz ÷1 ÷2 ÷4 ÷8 11 00 01 10 OE FOUT FOUT FB VCC XTAL_SEL ÷0 TO ÷511 9-BIT M-DIVIDER 9 VCC P_LOAD S_LOAD LE P/S 0 BITS 5-13 S_DATA S_CLOCK VCC 1 BITS 3-4 14-BIT SHIFT REGISTER 0 1 BITS 0-2 M-LATCH ÷2 2 N-LATCH TEST 3 T-LATCH TEST Freescale Semiconductor, Inc... M[0:8] N[1:0] OE Figure 1. MPC9230 Logic Diagram M[8] M[7] M[6] M[5] 18 FOUT TEST FOUT GND GND VCC VCC S_CLOCK S_DATA S_LOAD VCC_PLL FREF_EXT XTAL_SEL XTAL_IN 26 27 28 1 2 3 4 25 24 23 22 21 20 19 24 18 17 16 N[1] N[0] M[8] M[7] M[6] M[5] M[4] GND TEST VCC VCC GND FOUT FOUT VCC 25 26 27 28 29 30 31 32 1 23 22 21 20 19 M[4] 17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT 13 12 11 10.


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