9-BIT PARITY GENERATOR/CHECKER
HCC/HCF40101B
9-BIT PARITY GENERATOR/CHECKER
. . . . . .
STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CUR...
Description
HCC/HCF40101B
9-BIT PARITY GENERATOR/CHECKER
. . . . . .
STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N° 13A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF ”B” SERIES CMOS DEVICES”
EY (Plastic Package)
F (Ceramic Frit Seal Package)
M1 (Micro Package)
C1 (Plastic Chip Carrier)
ORDER CODES : HCC40101BF HCF40101BM1 HCF40101BEY HCF40101BC1
PIN CONNECTIONS
DESCRIPTION The HCC40101B (extended temperature range) and HCF40101B (intermediate temperature range) are monolithic integrated circuits, available in 14lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF40101B is a 9-bit (8 data bits plus 1 parity bit) parity generator/checker. It may be used to detect errors in data transmission or data retrieval. Odd and even outputs facilitate odd or even parity generation and checking. When used as a parity generator, a parity bit is supplied along with the data to generate an even or odd parity output. When used a parity checker, the received data bits and parity bits are compared for correct parity. The even or odd outputs are used to indicate an error in the received data. Word-length capability is expandable by cascading. The HCC/HCF40101B is also provided with an inhibit control. If the inhibit control is set at logical ”1”...
Similar Datasheet