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IDT74FCT824A Dataheets PDF



Part Number IDT74FCT824A
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
Datasheet IDT74FCT824A DatasheetIDT74FCT824A Datasheet (PDF)

® HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS DESCRIPTION: Integrated Device Technology, Inc. IDT54/74FCT821A/B/C IDT54/74FCT823A/B/C IDT54/74FCT824A/B/C IDT54/74FCT825A/B/C FEATURES: • Equivalent to AMD’s Am29821-25 bipolar registers in pinout/function, speed and output drive over full temperature and voltage supply extremes • IDT54/74FCT821A/823A/824A/825A equivalent to FAST™ speed • IDT54/74FCT821B/823B/824B/825B 25% faster than FAST • IDT54/74FCT821C/823C/824C/825C 40% faster than FAST.

  IDT74FCT824A   IDT74FCT824A


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® HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS DESCRIPTION: Integrated Device Technology, Inc. IDT54/74FCT821A/B/C IDT54/74FCT823A/B/C IDT54/74FCT824A/B/C IDT54/74FCT825A/B/C FEATURES: • Equivalent to AMD’s Am29821-25 bipolar registers in pinout/function, speed and output drive over full temperature and voltage supply extremes • IDT54/74FCT821A/823A/824A/825A equivalent to FAST™ speed • IDT54/74FCT821B/823B/824B/825B 25% faster than FAST • IDT54/74FCT821C/823C/824C/825C 40% faster than FAST • Buffered common Clock Enable (EN) and asynchronous Clear input (CLR) • IOL = 48mA (commercial) and 32mA (military) • Clamp diodes on all inputs for ringing suppression • CMOS power levels (1mW typ. static) • TTL input and output compatibility • CMOS output level compatible • Substantially lower input current levels than AMD’s bipolar Am29800 series (5µA max.) • Product available in Radiation Tolerant and Radiation Enhanced versions • Military product compliant to MIL-STD-883, Class B The IDT54/74FCT800 series is built using an advanced dual metal CMOS technology. The IDT54/74FCT820 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The IDT54/ 74FCT821 are buffered, 10-bit wide versions of the popular ‘374 function. The IDT54/74FCT823 and IDT54/74FCT824 are 9-bit wide buffered registers with Clock Enable (EN) and Clear (CLR) – ideal for parity bus interfacing in high-performance microprogrammed systems. The IDT54/74FCT825 are 8-bit buffered registers with all the ‘823 controls plus multiple enables (OE1, OE2, OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/WR. They are ideal for use as an output port requiring HIGH IOL/IOH. All of the IDT54/74FCT800 high-performance interface family are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state. FUNCTIONAL BLOCK DIAGRAMS IDT54/74FCT821/823/825 D0 EN DN IDT54/74FCT824 D0 EN DN CLR D CL Q D CL Q CLR D CL Q D CL Q CP Q CP Q CP Q CP Q CP CP OE Y0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. OE YN 2608 cnv* 01 Y0 YN 2608 cnv* 02 MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1992 Integrated Device Technology, Inc. MAY 1992 DSC-4618/2 7.19 1 IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS IDT54/74FCT821 10-BIT REGISTER OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 1 2 3 4 P24-1 5 D24-1 6 E24-1 & 7 SO24-2 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 CP D1 D0 OE NC VCC Y0 Y1 LOGIC SYMBOLS INDEX D2 D3 D4 NC D5 D6 D7 4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 20 10 19 11 1213 14 15 16 17 18 D8 D9 GND NC CP Y9 Y8 10 Y2 Y3 Y4 NC Y5 Y6 Y7 D D CP CP OE 10 Q Y DIP/SOIC/CERPACK TOP VIEW LCC TOP VIEW 2608 cnv* 03 IDT54/74FCT823/824 9-BIT REGISTERS OE D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND 1 2 3 4 P24-1 5 D24-1 6 SO24-2 & 7 E24-1 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 EN CP D2 D3 D4 NC D5 D6 D7 4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18 D1 D0 OE NC VCC Y0 Y1 INDEX Y2 Y3 Y4 NC Y5 Y6 Y7 D 9 Q CP EN CLR D 9 Y CP EN CLR OE DIP/SOIC/CERPACK TOP VIEW D8 CLR GND NC CP EN Y8 LCC TOP VIEW 2608 cnv* 04 IDT54/74FCT825 8-BIT REGISTER OE1 OE2 D0 D1 D2 D3 D4 D5 D6 D7 CLR GND 1 2 3 4 P24-1 5 D24-1 6 E24-1 & 7 8 SO24-2 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC OE3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 EN CP INDEX D0 OE2 OE1 NC VCC OE3 Y0 D D1 D2 D3 NC D4 D5 D6 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18 4 3 2 Y1 Y2 Y3 NC Y4 Y5 Y6 8 Q CP EN CLR D 8 Y CP EN CLR OE1 OE2 OE3 D7 CLR GND NC CP DIP/SOIC/CERPACK TOP VIEW LCC TOP VIEW EN Y7 2608 cnv* 05 7.19 2 IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES PRODUCT SELECTOR GUIDE Device 10-Bit Non-inverting Inverting FUNCTION TABLE(1) IDT54/74FCT821/823/825 8-Bit OE CLR 9-Bit 54/74FCT824A/B/C Inputs EN 54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C DI L H X X X X L H L H CP ↑ ↑ X X X X ↑ ↑ ↑ ↑ Internal/ Outputs QI YI L H L L NC NC L H L H Z Z Z L Z NC Z Z L H 2608 tbl 01 H H H L H L H H L L H H L L H H H H H H L L X X H H L L L L Function High Z Clear Hold Load PIN DESCRIPTION Name DI CLR I/O I I Description The D flip-flop data inputs. For both inverting and non-inverting registers, when the clear input is LOW and OE is LOW, the QI outputs are LOW. When the clear input is HIGH, data can be entered into the register. Clock Pulse for the Register; enters data into.


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